EVAL-AD5247DBZ Analog Devices, EVAL-AD5247DBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD5247DBZ
• Description: Digital Potentiometer Development Tools EVALUATION BOARD I.C.
• Manufacturer: Analog Devices
• Series: AD5247r

Specifications of EVAL-AD5247DBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD5247
• Resistance: 5 kOhms/10 kOhms/50 kOhms/100 kOhms
• Operating Supply Voltage: 5.5 V
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Factory Pack Quantity: 1
• For Use With: Sim DAC Web Tool

Data Sheet
Parameter
DYNAMIC CHARACTERISTICS
1
2
3
4
5
6
7
8
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS
V
Table 3.
Parameter
SCL Clock Frequency
Bus Free Time Between Stop and Start, t
Hold Time (Repeated Start), t
Low Period of SCL Clock, t
High Period of SCL Clock, t
Setup Time for Repeated Start Condition, t
Data Hold Time, t
Data Setup Time, t
Fall Time of Both SDA and SCL Signals, t
Rise Time of Both SDA and SCL Signals, t
Setup Time for Stop Condition, t
1
2
3
4
5
Typical specifications represent average readings at 25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
V
INL and DNL are measured at V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
Guaranteed by design, not subject to production test.
P
All dynamic characteristics use V
Specifications apply to all parts.
Guaranteed by design, not subject to production test.
See timing diagrams (Figure 2, Figure 33, and Figure 34) for locations of measured values.
Typical specifications represent average readings at 25°C and V
After this period, the first clock pulse is generated.
DD
A
DISS
Bandwidth –3 dB
Total Harmonic Distortion
V
Resistor Noise Voltage Density
= V
W
= 5 V ± 10% or 3 V ± 10%, V
is calculated from (I
Settling Time (10 kΩ/50 kΩ/100 kΩ)
DD
, wiper (V
SDA
SCL
1, 2, 3
P
W
) = no connect.
HD;DAT
SU;DAT
t
1
DD
S
× V
DD
LOW
HIGH
W,
6, 8
). CMOS logic level inputs result in minimum power dissipation.
t
2
DD
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
HD;STA
= 5 V.
SU;STO
5
A
= V
t
3
t
F
DD
8
BUF
R
, −40°C < T
SU;STA
t
8
t
Figure 2. I
9
Symbol
BW
THD
t
e
S
N_WB
A
DD
DD
t
6
< +125°C, unless otherwise noted.
= 5 V.
= 5 V.
W
2
C Interface, Detailed Timing Diagram
t
9
t
4
Rev. F | Page 5 of 20
Conditions
R
code = 0x40
V
V
R
AB
WB
A
A
=1 V rms, f = 1 kHz, R
= 5 V ±1 LSB error band
= 10 kΩ/50 kΩ/100 kΩ,
= 5 kΩ, R
t
7
S
= 0
Symbol
f
t
t
t
t
t
t
t
t
t
t
SCL
1
2
3
4
5
6
7
8
9
10
AB
= 10 kΩ
S
t
5
t
2
Min
1.3
0.6
1.3
0.6
0.6
100
0.6
Min
A
= V
DD
and V
Typ
Typ
600/100/40
0.05
2
9
4
B
1
= 0 V.
Max
400
50
0.9
300
300
t
10
Max
P
AD5247
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
Unit
kHz
%
µs
nV/√Hz