EVAL-AD5243SDZ Analog Devices, EVAL-AD5243SDZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD5243SDZ
• Description: Digital Potentiometer Development Tools EVALUATION BOARD
• Manufacturer: Analog Devices
• Series: AD5243r

Specifications of EVAL-AD5243SDZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD5243
• Resistance: 2.5 kOhms/10 kOhms/50 kOhms/100 kOhms
• Operating Supply Voltage: 5.5 V
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Factory Pack Quantity: 1
• For Use With: Sim DAC Web Tool

Data Sheet
TIMING CHARACTERISTICS: ALL VERSIONS
V
Table 3.
Parameter
I
1
2
2
See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 45 to Figure 48).
The maximum t
C INTERFACE TIMING CHARACTERISTICS
DD
SCL Clock Frequency
Bus-Free Time Between Stop and Start, t
Hold Time (Repeated Start), t
Low Period of SCL Clock, t
High Period of SCL Clock, t
Setup Time for Repeated Start Condition, t
Data Hold Time, t
Data Setup Time, t
Fall Time of Both SDA and SCL Signals, t
Rise Time of Both SDA and SCL Signals, t
Setup Time for Stop Condition, t
= 5 V ± 10%, or 3 V ± 10%; V
SCL
SDA
HD:DAT
P
must be met only if the device does not stretch the low period (t
HD;DAT
SU;DAT
t
1
2
S
LOW
HIGH
t
2
HD;STA
SU;STO
A
= V
t
3
DD
1
F
; V
BUF
R
t
8
SU;STA
B
t
8
= 0 V; −40°C < T
t
Figure 3. I
9
Symbol
f
t
t
t
t
t
t
t
t
t
t
SCL
1
2
3
4
5
6
7
8
9
10
t
6
2
C Interface Detailed Timing Diagram
t
4
t
Rev. B | Page 5 of 20
9
A
< +125°C; unless otherwise noted.
Conditions
After this period, the first clock pulse is
generated.
LOW
t
) of the SCL signal.
7
S
t
5
t
2
Min
0
1.3
0.6
1.3
0.6
0.6
100
0.6
AD5243/AD5248
Typ
P
t
10
Max
400
0.9
300
300
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs