AT25128B-SSHL-B Atmel, AT25128B-SSHL-B Datasheet - Page 9

• Manufacturer Part Number: AT25128B-SSHL-B
• Description: IC EEPROM 128KBIT 20MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25128B-SSHL-B

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 128K (16K x 8)
• Speed: 5MHz, 10MHz, 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Density: 128Kb
• Interface Type: Serial (SPI)
• Organization: 16Kx8
• Access Time (max): 80ns
• Frequency (max): 5MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Temp Range: -40C to 85C
• Supply Current: 10mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Memory Configuration: 16384 X 8
• Clock Frequency: 3MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8698B–SEEPR–3/10
WRITE SEQUENCE (WRITE): In order to program the AT25128B/256B, two separate instructions must be exe-
cuted. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write instruction
may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected
address field location selected by the Block Write Protection Level. During an internal write cycle, all commands
will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the Write
op-code is transmitted via the SI line followed by the byte address and the data (D7 - D0) to be programmed (see
Table 2-6
of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) Instruction. If
Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has ended. Only the Read Status Register
instruction is enabled during the Write programming cycle.
The AT25128B/256B is capable of a 64-byte Page Write operation. After each byte of data is received, the six low
order address bits are internally incremented by one; the high order bits of the address will remain constant. If
more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25128B/256B is automatically returned to the write disable state at the completion of a Write
cycle.
Note:
Table 3-6.
If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby
state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication.
Don’t Care Bits
for the address key). Programming will start after the CS pin is brought high. (The Low-to-High transition
Address
Address Key
A
N
AT25128B
A
A
15
13
− A
− A
14
0
AT25256B
A
14
A
− A
15
0
AT25128B/256B
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