AT24C128B-TH-T Atmel, AT24C128B-TH-T Datasheet - Page 9

• Manufacturer Part Number: AT24C128B-TH-T
• Description: IC EEPROM 128KBIT 1MHZ 8TSSOP
• Manufacturer: Atmel

Specifications of AT24C128B-TH-T

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 128K (16K x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8. Write Operations
5296A–SEEPR–1/08
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a “0”. The addressing device, such as a microcontroller, must
then terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally-timed write cycle, t
write cycle and the EEPROM will not respond until the write is complete (see
Figure 8-1.
Note:
PAGE WRITE: The 128K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 63 more data words. The
EEPROM will respond with a “0” after each data word received. The microcontroller must termi-
nate the page write sequence with a stop condition (see
Figure 8-2.
Note:
The data word address lower six bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the fol-
lowing byte is placed at the beginning of the same page. If more than 64 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “roll over” during write is from the last byte of the current page to the
first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a “0”, allowing the read or write sequence to continue.
*
*
= DON’T CARE bit
= DON’T CARE bit
Byte Write
Page Write
WR
, to the nonvolatile memory. All inputs are disabled during this
Figure
8-2).
AT24C128B
Figure
8-1).
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