AT45DB011D-SH-T Atmel, AT45DB011D-SH-T Datasheet - Page 21

• Manufacturer Part Number: AT45DB011D-SH-T
• Description: IC FLASH 1MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB011D-SH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 1M (512 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Data Bus Width: 8 bit
• Architecture: Sectored
• Interface Type: SPI Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 25 mA
• Mounting Style: SMD/SMT
• Organization: 32 KB x 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.2
11. Additional Commands
11.1
11.2
3639H–DFLASH–04/09
Main Memory Page to Buffer Transfer
Main Memory Page to Buffer Compare
Reading the Security Register
The Security Register can be read by first asserting the CS pin and then clocking in an opcode
of 77H followed by three dummy bytes. After the last don’t care bit has been clocked in, the con-
tent of the Security Register can be clocked out on the SO pins. After the last byte of the
Security Register has been read, additional pulses on the SCK pin will simply result in undefined
data being output on the SO pins.
Deasserting the CS pin will terminate the Read Security Register operation and put the SO pins
into a high-impedance state.
Figure 10-4. Read Security Register
A page of data can be transferred from the main memory to the buffer. To start the operation for
the DataFlash standard page size (264 bytes), a 1-byte opcode, 53H, must be clocked into the
device, followed by three address bytes comprised of 6 don’t care bits, 9 page address bits
(PA8 - PA0), which specify the page in main memory that is to be transferred, and 9 don’t care
bits. To perform a main memory page to buffer transfer for the binary page size (256 bytes), the
opcode 53H must be clocked into the device followed by three address bytes consisting of 7
don’t care bits, 9 page address bits (A16 - A8) which specify the page in the main memory that is
to be transferred, and 8 don’t care bits. The CS pin must be low while toggling the SCK pin to
load the opcode and the address bytes from the input pin (SI). The transfer of the page of data
from the main memory to the buffer will begin when the CS pin transitions from a low to a high
state. During the transfer of a page of data (t
whether the transfer has been completed.
A page of data in main memory can be compared to the data in the buffer. To initiate the opera-
tion for the DataFlash standard page size, a 1-byte opcode, 60H, must be clocked into the
device, followed by three address bytes consisting of 6 don’t care bits, 9 page address bits
(PA8 - PA0) that specify the page in the main memory that is to be compared to the buffer, and
9 don’t care bits. To start a main memory page to buffer compare for a binary page size, the
opcode 60H must be clocked into the device followed by three address bytes consisting of 6
don’t care bits, 9 page address bits (A16 - A8) that specify the page in the main memory that is
to be compared to the buffer, and 8 don’t care bits. The CS pin must be low while toggling the
SCK pin to load the opcode and the address bytes from the input pin (SI). On the low-to-high
transition of the CS pin, the data bytes in the selected main memory page will be compared with
CS
SO
SI
Each transition
represents 8 bits
Opcode
X
X
XFR
X
), the status register can be read to determine
Data Byte
n
Data Byte
n + 1
Data Byte
n + x
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