93LC56X-I/SN Microchip Technology, 93LC56X-I/SN Datasheet - Page 6

• Manufacturer Part Number: 93LC56X-I/SN
• Description: IC EEPROM 2KBIT 2MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 93LC56X-I/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8 or 128 x 16)
• Speed: 1MHz, 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

93LC46/56/66
2.0
When the ORG pin is connected to V
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instruc-
tions, addresses and write data are clocked into the
DI pin on the rising edge of the clock (CLK). The DO
pin is normally held in a high-Z state except when
reading data from the device, or when checking the
Ready/Busy status during a programming operation.
The Ready/Busy status can be verified during an
erase/write operation by polling the DO pin; DO low
indicates that programming is still in progress, while
DO high indicates the device is ready. The DO will
enter the high-Z state on the falling edge of the CS.
2.1
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device opera-
tion (Read, Write, Erase, EWEN, EWDS, ERAL and
WRAL). As soon as CS is high, the device is no longer
in the Standby mode.
An instruction following a Start condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become “don't care” bits until a new Start condition is
detected.
2.2
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
2.3
During power-up, all programming modes of operation
are inhibited until V
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
DS21712B-page 6
CC
has fallen below 1.4V at nominal conditions.
FUNCTIONAL DESCRIPTION
Start Condition
Data In/Data Out (DI/DO)
Data Protection
CC
has reached a level greater than
CC
, the (x16)
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
2.4
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16-bit (x16 organization) or 8-bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T
possible when CS is held high. The memory data will
automatically cycle to the next register and output
sequentially.
2.5
The 93LC46/56/66 power up in the Erase/Write Disable
(EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V
accidental data disturb, the EWDS instruction can be
used to disable all erase/write functions and should
follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and EWDS
instructions.
2.6
The ERASE instruction forces all data bits of the speci-
fied address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The erase cycle takes 4 ms per word typical.
CC
CSL
is removed from the device. To protect against
Read
Erase/Write Enable and Disable
(EWEN, EWDS)
Erase
). DO at logical “0” indicates that program-
 2004 Microchip Technology Inc.
PD
). Sequential read is