SIR401DP-T1-GE3 Vishay/Siliconix, SIR401DP-T1-GE3 Datasheet

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SIR401DP-T1-GE3

Manufacturer Part Number
SIR401DP-T1-GE3
Description
MOSFET -20V 3.2mOhm@10V 50A P-Ch G-III
Manufacturer
Vishay/Siliconix
Datasheet

Specifications of SIR401DP-T1-GE3

Product Category
MOSFET
Rohs
yes
Transistor Polarity
P-Channel
Drain-source Breakdown Voltage
- 20 V
Continuous Drain Current
- 50 A
Resistance Drain-source Rds (on)
3.2 mOhms
Configuration
Single
Mounting Style
SMD/SMT
Package / Case
PowerPAK SO-8
Fall Time
100 ns
Forward Transconductance Gfs (max / Min)
77 S
Gate Charge Qg
310 nC
Power Dissipation
39 W
Rise Time
130 ns
Typical Turn-off Delay Time
300 ns
Part # Aliases
SIR401DP-GE3

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SIR401DP-T1-GE3
Manufacturer:
VISHAY/威世
Quantity:
20 000
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. Maximum under steady state conditions is 70 °C/W.
d. Package limited.
e. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
f. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 63661
S12-0334-Rev. A, 13-Feb-12
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
PRODUCT SUMMARY
ABSOLUTE MAXIMUM RATINGS (T
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (T
Pulsed Drain Current (t = 300 µs)
Continuous Source-Drain Diode Current
Avalanche Current
Single-Pulse Avalanche Energy
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
Maximum Junction-to-Case
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
V
DS
- 20
(V)
Ordering Information:
SiR401DP-T1-GE3 (Lead (Pb)-free and Halogen-free)
0.0032 at V
0.0042 at V
0.0077 at V
8
6.15 mm
D
R
DS(on)
7
D
6
() Max.
D
GS
GS
GS
5
= - 4.5 V
= - 2.5 V
= - 10 V
J
D
= 150 °C)
PowerPAK SO-8
a, c
Bottom View
1
S
P-Channel 20 V (D-S) MOSFET
2
I
S
D
- 50
- 50
- 50
(A)
3
S
d
5.15 mm
This document is subject to change without notice.
4
e, f
G
Q
A
g
97 nC
= 25 °C, unless otherwise noted)
(Typ.)
Steady State
New Product
t 10 s
T
T
T
T
T
T
L = 0.1 mH
T
T
T
T
C
C
A
A
C
A
C
C
A
A
= 25 °C
= 70 °C
= 25 °C
= 25 °C
= 70 °C
= 25 °C
= 70 °C
= 25 °C
= 25 °C
= 70 °C
FEATURES
APPLICATIONS
• Halogen-free According to IEC 61249-2-21
• TrenchFET
• 100% R
• Compliant to RoHS Directive 2002/95/EC
• Adaptor Switch
• Battery Switch
• Load Switch
Definition
Symbol
R
R
thJA
thJC
Symbol
T
J
V
V
E
I
I
P
, T
I
DM
I
AS
DS
GS
AS
D
S
g
D
stg
and UIS Tested
®
Power MOSFET
P-Channel MOSFET
Typical
2.1
20
G
- 55 to 150
- 23.5
- 4.5
- 29
- 35.5
3.2
Limit
- 50
- 50
± 12
Maximum
5
- 20
- 80
- 30
260
45
39
25
a, b
a, b
a, b
a, b
a, b
3.2
d
d
25
Vishay Siliconix
S
D
d
www.vishay.com/doc?91000
SiR401DP
www.vishay.com
°C/W
Unit
Unit
mJ
°C
W
V
A
1

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SIR401DP-T1-GE3 Summary of contents

Page 1

... Bottom View Ordering Information: SiR401DP-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS (T Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (T = 150 °C) J Pulsed Drain Current (t = 300 µs) Continuous Source-Drain Diode Current Avalanche Current Single-Pulse Avalanche Energy ...

Page 2

... SiR401DP Vishay Siliconix SPECIFICATIONS ( °C, unless otherwise noted) J Parameter Static Drain-Source Breakdown Voltage V Temperature Coefficient DS V Temperature Coefficient GS(th) Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current a On-State Drain Current a Drain-Source On-State Resistance a Forward Transconductance b Dynamic Input Capacitance Output Capacitance ...

Page 3

... V C rss 1 1.4 1 1.0 0.8 0 168 210 On-Resistance vs. Junction Temperature This document is subject to change without notice. SiR401DP Vishay Siliconix = 25 ° ° 0.6 1.2 1.8 2.4 3 Gate-to-Source Voltage (V) GS Transfer Characteristics C iss C oss Drain-to-Source Voltage (V) ...

Page 4

... SiR401DP Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 100 = 150 ° ° 0.1 0.01 0.001 0.0 0.2 0.4 0.6 0 Source-to-Drain Voltage (V) SD Source-Drain Diode Forward Voltage 0.8 0.6 0 250 μ 0 100 T - Temperature (°C) J Threshold Voltage 100 10 0.1 0.01 www.vishay.com 4 THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT New Product 0 ...

Page 5

... Case Temperature (°C) C Current Derating* 2.5 2.0 1.5 1.0 0.5 0.0 125 150 0 Power Derating, Junction-to-Ambient = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper This document is subject to change without notice. SiR401DP Vishay Siliconix 150 100 125 150 T - Ambient Temperature (°C) A www.vishay.com www.vishay.com/doc?91000 5 ...

Page 6

... SiR401DP Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Duty Cycle = 0.5 0.2 0.1 0.05 0.1 0.02 Single Pulse 0.01 0.0001 0.001 Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of al valified locations ...

Page 7

PowerPAK SO-8, (SINGLE/DUAL Notes 1. Inch will govern. 2 Dimensions exclusive of mold gate burrs. 3. Dimensions exclusive of mold flash and cutting burrs. DIM. MIN. A 0.97 A1 0.00 b ...

Page 8

... PowerPAK thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Sili- conix MOSFETs. Click on the PowerPAK SO-8 single in the index of this document. In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. ...

Page 9

... Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this doc- ument. The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the Pow- erPAK SO-8 dual package ...

Page 10

THERMAL PERFORMANCE Introduction A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rθ junction-to-foot thermal resistance, Rθ is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device ...

Page 11

AN821 Vishay Siliconix SYSTEM AND ELECTRICAL IMPACT OF PowerPAK SO-8 In any design, one must take into account the change in MOSFET r with temperature (Figure 7). DS(on) On-Resistance vs. Junction Temperature 1 1.6 I ...

Page 12

RECOMMENDED MINIMUM PADS FOR PowerPAK 0.024 (0.61) 0.026 (0.66) 0.050 (1.27) Return to Index Return to Index Document Number: 72599 Revision: 21-Jan-08 ® SO-8 Single 0.260 (6.61) 0.150 (3.81) 0.032 (0.82) Recommended Minimum Pads Dimensions in Inches/(mm) Application Note 826 ...

Page 13

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), ...

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