MAX3206EEWL+T Maxim Integrated, MAX3206EEWL+T Datasheet - Page 6

• Manufacturer Part Number: MAX3206EEWL+T
• Description: TVS Diode Arrays Low-Capacitance, 2/3 /4/6-Channel, +-15kV
• Manufacturer: Maxim Integrated
• Series: MAX3202E, MAX3203E, MAX3204E, MAX3206Er

Specifications of MAX3206EEWL+T

• Rohs: yes
• Channels: 6 Channels
• Operating Voltage: 0.9 V to 5.5 V
• Termination Style: SMD/SMT
• Capacitance: 5 pF
• Dimensions: 4 mm W x 4 mm L x 0.75 mm H
• Peak Pulse Power Dissipation: 1349 mW

Figure 6. IEC 61000-4-2 ESD Test Model
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. The MAX3202E/
MAX3203E/MAX3204E/MAX3206E help users design
equipment that meets Level 4 of IEC 61000-4-2.
The main difference between tests done using the
Human Body Model and IEC 61000-4-2 is higher peak
current in IEC 61000-4-2. Because series resistance is
lower in the IEC 61000-4-2 ESD test model (Figure 6)
the ESD-withstand voltage measured to this standard is
generally lower than that measured using the Human
Body Model. Figure 3 shows the current waveform for
the ±8kV IEC 61000-4-2 Level 4 ESD Contact
Discharge test.
Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD
Protection Arrays for High-Speed Data Interfaces
6
VOLTAGE
SOURCE
_______________________________________________________________________________________
HIGH-
DC
CHARGE-CURRENT-
LIMIT RESISTOR
50Ω to 100Ω
R
C
150pF
C s
STORAGE
CAPACITOR
RESISTANCE
DISCHARGE
330Ω
R
D
IEC 61000-4-2
DEVICE
UNDER
TEST
The Air-Gap Discharge test involves approaching the
device with a charged probe. The Contact Discharge
method connects the probe to the device before the
probe is energized.
Proper circuit-board layout is critical to suppress ESD-
induced line transients. The MAX3202E/MAX3203E/
MAX3204E/MAX3206E clamp to 100V; however, with
improper layout, the voltage spike at the device is
much higher. A lead inductance of 10nH with a 45A
current spike at a dv/dt of 1ns results in an ADDITION-
AL 450V spike on the protected line. It is essential that
the layout of the PC board follows these guidelines:
1) Minimize trace length between the connector or
2) Use separate planes for power and ground to reduce
3) Ensure short ESD transient return paths to GND
4) Minimize conductive power and ground loops.
5) Do not place critical signals near the edge of the
6) Bypass V
7) Bypass the supply of the protected device to GND
input terminal, I/O_, and the protected signal line.
parasitic inductance and to reduce the impedance to
the power rails for shunted ESD current.
and V
PC board.
itor as close to V
with a low-ESR ceramic capacitor as close to the
supply pin as possible.
CC
.
CC
to GND with a low-ESR ceramic capac-
CC
Layout Recommendations
as possible.