MAX3206EEWL+T Maxim Integrated, MAX3206EEWL+T Datasheet - Page 4

• Manufacturer Part Number: MAX3206EEWL+T
• Description: TVS Diode Arrays Low-Capacitance, 2/3 /4/6-Channel, +-15kV
• Manufacturer: Maxim Integrated
• Series: MAX3202E, MAX3203E, MAX3204E, MAX3206Er

Specifications of MAX3206EEWL+T

• Rohs: yes
• Channels: 6 Channels
• Operating Voltage: 0.9 V to 5.5 V
• Termination Style: SMD/SMT
• Capacitance: 5 pF
• Dimensions: 4 mm W x 4 mm L x 0.75 mm H
• Peak Pulse Power Dissipation: 1349 mW

Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD
Protection Arrays for High-Speed Data Interfaces
The MAX3202E/MAX3203E/MAX3204E/MAX3206E are
diode arrays designed to protect sensitive electronics
against damage resulting from ESD conditions or tran-
sient voltages. The low input capacitance makes these
devices ideal for high-speed data lines. The
MAX3202E, MAX3203E, MAX3204E, and MAX3206E
protect two, three, four, and six channels, respectively.
The MAX3202E/MAX3203E/MAX3204E/MAX3206E are
designed to work in conjunction with a device’s intrinsic
ESD protection. The MAX3202E/MAX3203E/MAX3204E/
MAX3206E limit the excursion of the ESD event to
below ±25V peak voltage when subjected to the
Human Body Model waveform. When subjected to the
IEC 61000-4-2 waveform, the peak voltage is limited to
±60V when subjected to Contact Discharge and ±100V
when subjected to Air-Gap Discharge. The device that
is being protected by the MAX3202E/MAX3203E/
MAX3204E/MAX3206E must be able to withstand these
peak voltages plus any additional voltage generated by
the parasitic board.
Maximum protection against ESD damage results from
proper board layout (see the Layout Recommendations
section and Figure 2). A good layout reduces the para-
sitic series inductance on the ground line, supply line,
and protected signal lines.
The MAX3202E/MAX3203E/MAX3204E/MAX3206E ESD
diodes clamp the voltage on the protected lines during
an ESD event and shunt the current to GND or V
an ideal circuit, the clamping voltage, V
the forward voltage drop, V
plus any supply voltage present on the cathode.
For positive ESD pulses:
For negative ESD pulses:
In reality, the effect of the parasitic series inductance
on the lines must also be considered (Figure 1).
For positive ESD pulses:
4
_______________________________________________________________________________________
Applications Information
V
C
Detailed Description
V
= V
C
Design Considerations
= -V
CC
F
, of the protection diode
+ V
F
F
C
, is defined as
CC
. In
For negative ESD pulses:
where I
Figure 1. Parasitic Series Inductance
Figure 2. Layout Considerations
V
V
C
C
V
PROTECTED LINE
NEGATIVE ESD
CURRENT
PULSE
PATH TO
GROUND
GND
CC
=
= −
V
ESD
CC
⎛
⎜
⎝
V
PROTECTED
LINE
L1
F D
is the ESD current pulse.
+
( )
V
2
F D
( )
+
1
L1
POSITIVE SUPPLY RAIL
⎛
⎝ ⎜
+
L x
D1
D2
1
⎛
⎝ ⎜
L x
I/O_
1
d I
L2
L3
GROUND RAIL
(
I/O_
D1
D2
ESD
dt
d I
(
L2
L3
ESD
dt
)
⎞
⎠ ⎟
+
)
⎞
⎠ ⎟
⎛
⎝ ⎜
+
L x
V
3
C
⎛
⎝ ⎜
L
2
d
x
PROTECTED
(
CIRCUIT
I I
d I
ESD
dt
(
ESD
dt
)
⎞
⎠ ⎟
)
⎞
⎟
⎠
⎞
⎠ ⎟