24LC32A/SM Microchip Technology, 24LC32A/SM Datasheet - Page 6
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24LC32A/SM
Manufacturer Part Number
24LC32A/SM
Description
IC EEPROM 32KBIT 400KHZ 8SOIC
Manufacturer
Microchip Technology
Specifications of 24LC32A/SM
Memory Size
32K (4K x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Memory Configuration
4K X 8
Ic Interface Type
I2C
Clock Frequency
400kHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
SOIC
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
24AA32A/24LC32A
3.6
A control byte is the first byte received following the
Start condition from the master device (Figure 3-2).
The control byte consists of a four-bit control code. For
the 24XX32A, this is set as ‘1010’ binary for read and
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select
bits allow the use of up to eight 24XX32A devices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 3-3). Because
only A11 to A0 are used, the upper four address bits are
“don’t care” bits. The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX32A monitors
the SDA bus checking the device type identifier being
transmitted and, upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX32A will select a read
or write operation.
FIGURE 3-3:
DS21713H-page 6
1
Control
Code
0
Device Addressing
1
Control Byte
0
A
2
Select
ADDRESS SEQUENCE BIT ASSIGNMENTS
Chip
Bits
A
1
A
0 R/W
x
x
Address High Byte
x
x
11
A
10
A
FIGURE 3-2:
3.7
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 256K
bits by adding up to eight 24XX32A devices on the
same bus. In this case, software can use A0 of the con-
trol byte as address bit A12; A1 as address bit A13; and
A2 as address bit A14. It is not possible to sequentially
read across device boundaries.
A
9
Start Bit
S
A
8
Contiguous Addressing Across
Multiple Devices
1
Control Code
0
A
7
Slave Address
•
1
Address Low Byte
CONTROL BYTE FORMAT
© 2007 Microchip Technology Inc.
•
0
•
Read/Write Bit
Chip Select
A2 A1 A0
Acknowledge Bit
•
Bits
x = “don’t care” bit
•
•
A
0
R/W
ACK