AT24C04BN-SH-T Atmel, AT24C04BN-SH-T Datasheet - Page 6

• Manufacturer Part Number: AT24C04BN-SH-T
• Description: IC EEPROM 4KBIT 1MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT24C04BN-SH-T

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 512 K x 8
• Interface Type: 2-Wire
• Maximum Clock Frequency: 1 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.
6
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (see
start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (see
STOP CONDITION:
command will place the EEPROM in a standby power mode (see
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C04B/08B features a low-power standby mode which is enabled:
2-WIRE SOFTWARE RESET: After
2-wire part can be reset by following these steps:
Figure 3.
AT24C04B/08B
SCL
SDA
(a) Upon power-up and
(b) After the receipt of the STOP bit and the completion of any internal operations.
(a) Create a start bit condition,
(b)
(c) Create another start bit followed by a stop bit condition as shown below. The device is ready for the next
communication after the above steps have been completed.
Clock 9 cycles,
Start bit
Software reset
Figure
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
7).
1
2
an
interruption
Dummy Clock Cycles
3
Figure 6
in
). Data changes during SCL high periods will indicate a
protocol,
Figure
8
7).
power
9
loss
Start bit
or
system
5226G–SEEPR–11/09
reset,
Stop bit
any