SST89E554RC-40-I-PI Microchip Technology, SST89E554RC-40-I-PI Datasheet - Page 49
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SST89E554RC-40-I-PI
Manufacturer Part Number
SST89E554RC-40-I-PI
Description
8-bit Microcontrollers - MCU 32KB+8KB 40ns
Manufacturer
Microchip Technology
Datasheet
1.SST89E564RD-40-I-NJE.pdf
(90 pages)
Specifications of SST89E554RC-40-I-PI
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Program Memory Size
32 KB
Data Ram Size
1 KB
Operating Supply Voltage
4.5 V to 5.5 V
Package / Case
PDIP-40
Mounting Style
Through Hole
Data Rom Size
128 B
Interface Type
SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
32
Number Of Timers
16 bit
Processor Series
FlashFlex
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SST89E554RC-40-I-PI
Manufacturer:
MAXIM
Quantity:
24
FlashFlex MCU
SST89E564RD / SST89V564RD
SST89E554RC / SST89V554RC
7.0 WATCHDOG TIMER
The device offers a programmable Watchdog Timer (WDT)
for fail safe protection against software deadlock and auto-
matic recovery.
To protect the system against software deadlock, the user
software must refresh the WDT within a user-defined time
period. If the software fails to do this periodical refresh, an
internal hardware reset will be initiated if enabled (WDRE=
1). The software can be designed such that the WDT times
out if the program does not work properly.
The WDT in the device uses the system clock (XTAL1) as
its time base. So strictly speaking, it is a watchdog counter
rather than a watchdog timer. The WDT register will incre-
ment every 344,064 crystal clocks. The upper 8-bits of the
time base register (WDTD) are used as the reload register
of the WDT.
©2007 Silicon Storage Technology, Inc.
FIGURE
Ext. RST
CLK (XTAL1)
7-1: B
WDTC
LOCK
D
IAGRAM OF
Counter
P
ROGRAMMABLE
344064
clks
WDT Upper Byte
49
WDTD
W
ATCHDOG
The WDTS flag bit is set by WDT overflow and is not
changed by WDT reset. User software can clear WDTS by
writing “1” to it.
Figure 7-1 provides a block diagram of the WDT. Two SFRs
(WDTC and WDTD) control watchdog timer operation.
During idle mode, WDT operation is temporarily sus-
pended, and resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
where WDTD is the value loaded into the WDTD register
and f
OSC
Period = (255 - WDTD) * 344064 * 1/f
is the oscillator frequency.
T
WDT Reset
IMER
1207 F18.0
Internal Reset
S71207-08-EOL
EOL Data Sheet
CLK (XTAL1)
1/07