CAT25040VI-GT3 ON Semiconductor, CAT25040VI-GT3 Datasheet - Page 8

• Manufacturer Part Number: CAT25040VI-GT3
• Description: IC EEPROM 4KBIT 10MHZ 8SOIC
• Manufacturer: ON Semiconductor

Specifications of CAT25040VI-GT3

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 25040VI-GT3; CAT25040VI-GT3TR

Read from Memory Array
followed by a 8−bit address (for the CAT25040, bit 3 of the
read instruction opcode contains A8 address bit).
will respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
SCK
SCK
To read from memory, the host sends a READ instruction
After receiving the last address bit, the CAT25010/20/40
CS
CS
SO
SO
SI
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
0
0
0
0
0
1
0
0
2
1
0
3
HIGH IMPEDANCE
OPCODE
OPCODE
0
X*
2
4
0
0
HIGH IMPEDANCE
5
3
1
6
0
4
1
7
A
8
7
1
5
Figure 10. RDSR Timing
Figure 9. READ Timing
READ OPERATIONS
http://onsemi.com
9
BYTE ADDRESS
6
0
1
8
7
12
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Status Register
command. After receiving the last bit of the command, the
CAT25010/20/40 will shift out the contents of the status
register on the SO pin (Figure 10). The status register may
be read at any time, including during an internal write cycle.
While the internal write cycle is in progress, the RDSR
command will output the RDY (Ready) bit status only (i.e.,
data out = FFh).
MSB
13
To read the status register, the host simply sends a RDSR
8
7
14 15 16 17 18 19
9
6
A
0
10
5
MSB
D7 D6 D5 D4 D3 D2 D1 D0
11
4
DATA OUT
12
3
DATA OUT
20 21 22
13
2
14
1
0