MR0A08BYS35 EverSpin Technologies Inc, MR0A08BYS35 Datasheet - Page 11
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MR0A08BYS35
Manufacturer Part Number
MR0A08BYS35
Description
IC MRAM 1MBIT 35NS 44TSOP
Manufacturer
EverSpin Technologies Inc
Datasheet
1.MR0A08BYS35.pdf
(15 pages)
Specifications of MR0A08BYS35
Format - Memory
RAM
Memory Type
MRAM (Magnetoresistive RAM)
Memory Size
1M (128K x 8)
Speed
35ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
44-TSOP II
Word Size
8b
Organization
128Kx8
Density
1Mb
Interface Type
Parallel
Access Time (max)
35ns
Operating Supply Voltage (typ)
3.3V
Operating Temperature Classification
Commercial
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 70C
Pin Count
44
Mounting
Surface Mount
Supply Current
65mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
819-1002
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MR0A08BYS35R
Manufacturer:
EVERSPIN
Quantity:
20 000
Everspin Technologies © 2009
Timing Specifications
1
2
3
All write cycle timings are referenced from the last valid address to the first transition address.
Parameter
Write cycle time
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Write pulse width
Data valid to end of write
Data hold time
Enable recovery time
Write recovery time
Write to enable recovery time
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W, or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
If E goes low at the same time or after W goes low the output will remain in a high impedance state. If E goes high at the same
time or before W goes high the output will remain in a high impedance state. E must be brought high each cycle.
W (WRITE ENABLE)
E (CHIP ENABLE)
A (ADDRESS)
D (DATA IN)
2
Table 3.6 Write Cycle Timing 3 (Shortened t
Table 3.6 Write Cycle Timing 3 (Shortened t
3
3
t
AVWL
11
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
AVAV
AVWL
AVWH
AVWH
WLWH
WLEH
DVWH
WHDX
EHAX
WHAX
WHEL
AVWH
t
AVAV
t
WLWH
t
WLEH
Document Number: MR0A08B Rev. 2, 6/2009
WHAX
WHAX
, W and E Controlled)
Min
35
0
18
20
15
10
0
-2
6
12
, W and E Controlled)
t
DVWH
Max
-
-
-
-
-
-
-
-
-
-
t
WHDX
t
t
WHEL
WHAX
MR0A08B
t
EHAX
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns