ST72T331N2T6 STMicroelectronics, ST72T331N2T6 Datasheet - Page 24

• Manufacturer Part Number: ST72T331N2T6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72T331N2T6

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 8
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• On-chip Dac: No
• Program Memory Type: EPROM
• Factory Pack Quantity: 90
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.5 V

ST72E331 ST72T331
4.4 POWER SAVING MODES
4.4.1 Introduction
There are three Power Saving modes. Slow Mode
is selected by setting the relevant bits in the Mis-
cellaneous register. Wait and Halt modes may be
entered using the WFI and HALT instructions.
4.4.2 Slow Mode
In Slow mode, the oscillator frequency can be di-
vided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.
4.4.3 Wait Mode
Wait mode places the MCU in a low power con-
sumption mode by stopping the CPU. All peripher-
als remain active. During Wait mode, the I bit (CC
Register) is cleared, so as to enable all interrupts.
All other registers and memory remain unchanged.
The MCU will remain in Wait mode until an Inter-
rupt or Reset occurs, whereupon the Program
Counter branches to the starting address of the In-
terrupt or Reset Service Routine.
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.
Refer to
24/107
24
Figure 18
below.
Figure 18. WAIT Flow Chart
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
N
INTERRUPT
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
N
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
OR SERVICE INTERRUPT
I-BIT
FETCH RESET VECTOR
WFI INSTRUCTION
4096 CPU CLOCK
CYCLES DELAY
RESET
Y
ON
ON
OFF
CLEARED
ON
ON
ON
ON
SET
ON
ON
SET