ST72T213G1B6 STMicroelectronics, ST72T213G1B6 Datasheet - Page 39

• Manufacturer Part Number: ST72T213G1B6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 4K SPI
• Manufacturer: STMicroelectronics

Specifications of ST72T213G1B6

• Rohs: yes
• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 5.5 V
• Package / Case: PDIP-32
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 6
• Interface Type: SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• On-chip Dac: No
• Program Memory Type: OTP EPROM
• Factory Pack Quantity: 16
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.5 V

16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OC i HR reg-
2. If the OC i E bit is not set, the OCMP i pin is a
3. When the timer clock is f
4. The output compare functions can be used both
5. The value in the 16-bit OC
Figure 28. Output Compare Block Diagram
16-bit
ister, the output compare function is inhibited
until the OC i LR register is also written.
general I/O port and the OLVL i bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMP i are set while the counter value equals
the OC i R register value (see
behaviour is the same in OPM or PWM mode.
When the timer clock is f
external clock mode, OCF i and OCMP i are set
while the counter value equals the OC i R regis-
ter value plus 1 (see
for generating external events on the OCMP i
pins even if the input capture mode is also
used.
OLV i bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
16 BIT FREE RUNNING
OC1R Register
OUTPUT COMPARE
16-bit
CIRCUIT
OC2R Register
COUNTER
16-bit
Figure
CPU
9).
i
R register and the
CPU
/4, f
Figure
/2, OCF i and
OC1E
CPU
OCIE
OC2E
OCF1
8). This
/8 or in
FOLV2 FOLV1
Forced Compare Output capability
When the FOLV i bit is set by software, the OLVL i
bit is copied to the OCMP i pin. The OLV i bit has to
be toggled in order to toggle the OCMP i pin when
it is enabled (OC i E bit=1). The OCF i bit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVL i bits have no effect in either One-Pulse
mode or PWM mode.
(Control Register 2) CR2
(Control Register 1) CR1
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
ST72101/ST72212/ST72213
OLVL1
0
Latch
Latch
1
2
39
OCMP1
OCMP2
Pin
Pin
39/85