CY7C138-25JXI Cypress Semiconductor Corp, CY7C138-25JXI Datasheet - Page 9

• Manufacturer Part Number: CY7C138-25JXI
• Description: IC SRAM 32KBIT 25NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C138-25JXI

• Memory Size: 32K (4K x 8)
• Package / Case: 68-PLCC
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 25 ns
• Maximum Clock Frequency: 1 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 180 mA
• Organization: 4 K x 8
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Waveforms
Notes
Document #: 38-06037 Rev. *G
24. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
25. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
26. R/W must be HIGH during all address transitions.
27. Data I/O pins enter high impedance when OE is held LOW during write.
SEM OR CE
SEM OR CE
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
placed on the bus for the required t
be as short as the specified t
Data Out
Address
Data Out
Address
Data In
Data In
R/W
R/W
OE
Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)
Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)
PWE
.
SD
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can
(continued)
t
SA
t
t
HZOE
SA
t
SCE
t
SCE
t
AW
t
High Impedance
AW
t
HZWE
t
WC
t
WC
t
PWE
t
PWE
PWE
t
SD
Data Valid
t
SD
or (t
High Impedance
Data Valid
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data to be
t
HD
t
t
HD
LZWE
t
HA
[24, 25, 26]
t
LZOE
[24, 26, 27]
t
HA
CY7C138
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