CY7C144AV-25AC Cypress Semiconductor Corp, CY7C144AV-25AC Datasheet - Page 9

• Manufacturer Part Number: CY7C144AV-25AC
• Description: IC SRAM 64KB DUAL 64-TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C144AV-25AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 64K (8K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Characteristics
Data Retention Mode
The
CY7C139AV/145AV/016AV/017AV are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
Notes:
Document #: 38-06051 Rev. *C
20. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
21. Test conditions used are Load 2.
22. t
23. CE = V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. Chip enable (CE) must be held HIGH during data retention,
2. CE must be kept between V
3. The RAM can begin operation >t
HD
HZWE
LZWE
WDD
DDD
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
INS
INR
SOP
SWRD
SPS
SAA
BUSY TIMING
INTERRUPT TIMING
SEMAPHORE TIMING
within V
during the power-up and power-down transitions.
minimum operating voltage (3.0 volts).
BDD
Parameter
[22]
[20]
[20]
[18, 19]
[18, 19]
is a calculated parameter and is the greater of t
CC
, V
CC
in
CY7C0138AV/144AV/006AV/007AV
= GND to V
to V
[21]
CC
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
– 0.2V.
CC
[21]
, T
A
= 25°C. This parameter is guaranteed but not tested.
CC
– 0.2V and 70% of V
Over the Operating Range
RC
after V
Description
WDD
–t
PWE
CC
(actual) or t
reaches the
CC
DDD
and
–t
SD
[15]
(actual).
(continued)
Timing
V
CE
ICC
CC
Parameter
DR1
Min.
15
10
0
3
5
0
5
5
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
-20
CY7C007AV/017AV
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
3.0V
Max.
12
40
30
20
20
20
16
20
20
20
20
@ VCC
Data Retention Mode
Test Conditions
V
CC
V
to V
CC
DR
> 2.0V
CY7C007AV/017AV
Min.
CC
17
12
= 2V
0
5
0
5
5
3
– 0.2V
-25
[23]
3.0V
Max.
50
35
20
17
25
20
20
15
20
20
25
Max.
50
V
Page 9 of 20
t
IH
RC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
µA