CY7C024A-25JXC Cypress Semiconductor Corp, CY7C024A-25JXC Datasheet - Page 10

• Manufacturer Part Number: CY7C024A-25JXC
• Description: IC SRAM 64KBIT 25NS 84PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C024A-25JXC

• Memory Size: 64K (4K x 16)
• Package / Case: 84-PLCC
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Maximum Clock Frequency: 1 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 190 mA
• Organization: 4 K x 16
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Characteristics
Data Retention Mode
The CY7C024/024A/0241 is designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules insure data retention:
Document #: 38-06035 Rev. *D
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. Chip enable (CE) must be held HIGH during data retention,
2. CE must be kept between V
3. The RAM can begin operation >t
Notes
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
INS
INR
SOP
SWRD
SPS
SAA
20. Test conditions used are Load 2.
21. t
22. CE = V
Parameter
Busy Timing
Interrupt Timing
Semaphore Timing
within V
the power up and power down transitions.
minimum operating voltage (4.5V).
BDD
[21]
is a calculated parameter and is the greater of t
CC
CC
, V
in
to V
= GND to V
BUSY LOW from Address
Match
BUSY HIGH from Address
Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Setup for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH
(Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or
SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
[20]
CC
[20]
– 0.2V.
CC
Description
, T
A
= 25°C. This parameter is guaranteed but not tested.
CC
– 0.2V and 70% of V
RC
Over the Operating Range (continued)
after V
WDD
CC
7C024/024A/0241–15
Min
–
7C025/0251–15
reaches the
13
10
5
5
0
5
t
PWE
CC
(actual) or t
Note 21
during
Max
15
15
15
15
15
15
15
DDD
7C024/024A/0241–25
–
t
Min
Timing
SD
V
7C025/0251–25
20
12
10
10
CE
ICC
5
0
CC
(actual).
Parameter
DR1
Note 21
[14]
Max
20
20
20
20
20
20
25
7C024/024A/0241–35
4.5V
At VCC
Min
Data Retention Mode
7C025/0251–35
10
30
15
10
5
0
Test Conditions
V
CC
V
to V
CC
DR
Note 21
> 2.0V
CC
CY7C024/024A/0241
Max
= 2V
35
20
20
20
20
25
25
– 0.2V
7C024/024A/0241–55
[22]
CY7C025/0251
4.5V
Min
7C025/0251–55
40
20
15
15
5
0
Max
1.5
Note 21
V
t
IH
Page 10 of 21
Max
RC
45
40
40
35
30
30
55
Unit
mA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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