CAT28C64BLI12 ON Semiconductor, CAT28C64BLI12 Datasheet - Page 7

IC EEPROM 64KBIT 120NS 28DIP

CAT28C64BLI12

Manufacturer Part Number
CAT28C64BLI12
Description
IC EEPROM 64KBIT 120NS 28DIP
Manufacturer
ON Semiconductor
Datasheet

Specifications of CAT28C64BLI12

Format - Memory
EEPROMs - Parallel
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
120ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
28C64BLI-12
CAT28C64BLI-12
CAT28C64BLI-12
DEVICE OPERATION
Read
Data stored in the CAT28C64B is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architec-
ture can be used to eliminate bus contention in a system
environment.
Figure 3. Read Cycle
Figure 4. Byte Write Cycle [WE Controlled]
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
ADDRESS
DATA OUT
DATA IN
WE
OE
CE
ADDRESS
DATA OUT
WE
OE
CE
t AS
t OES
V IH
HIGH-Z
t CS
t AH
t LZ
t RC
t CE
t OLZ
t WP
DATA VALID
t OE
HIGH-Z
7
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
DATA VALID
t OH
t CH
t OEH
t BLC
t AA
t WC
DATA VALID
t OHZ
t HZ
Doc. No. MD-1011, Rev. I
CAT28C64B

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