CAT24C256LI-G ON Semiconductor, CAT24C256LI-G Datasheet - Page 8

• Manufacturer Part Number: CAT24C256LI-G
• Description: IC EEPROM 256KBIT 400KHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT24C256LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 32 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Density: 256Kb
• Access Time (max): 500ns
• Frequency (max): 1MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Package Type: PDIP
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 24C256LI-G

CAT24C256
READ OPERATIONS
Immediate Address Read
In standby mode, the CAT24C256 internal address
counter points to the data byte immediately following the
last byte accessed by a previous operation. If that ‘previ-
ous’ byte was the last byte in memory, then the address
st
counter will point to the 1
memory byte, etc.
When, following a START, the CAT24C256 is presented
with a Slave address containing a ‘1’ in the R/W bit
th
position (Figure 9), it will acknowledge (ACK) in the 9
clock cycle, and will then transmit data being pointed
at by the internal address counter. The Master can stop
further transmission by issuing a NoACK, followed by a
STOP condition.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address
counter. The address counter can be initialized by per-
forming a ‘dummy’ Write operation (Figure 10). Here the
START is followed by the Slave address (with the R/W
bit set to ‘0’) and the desired two byte address. Instead
nd
of following up with data, the Master then issues a 2
START, followed by the ‘Immediate Address Read’ se-
quence, as described earlier.
Sequential Read
st
If the Master acknowledges the 1
data byte transmitted
by the CAT24C256, then the device will continue trans-
mitting as long as each data byte is acknowledged by
the Master (Figure 11). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap-around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting
byte address.
© 2008 SCILLC. All rights reserved
Doc. No. MD-1104, Rev. G
8
Characteristics subject to change without notice