CAT24C256LI-G ON Semiconductor, CAT24C256LI-G Datasheet - Page 4

• Manufacturer Part Number: CAT24C256LI-G
• Description: IC EEPROM 256KBIT 400KHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT24C256LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 32 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Density: 256Kb
• Access Time (max): 500ns
• Frequency (max): 1MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Package Type: PDIP
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 24C256LI-G

POWER-ON RESET (POR)
The CAT24C256 Die Rev. C incorporates Power-On
Reset (POR) circuitry which protects the internal logic
against powering up in the wrong state.
The device will power up into Standby mode after V
exceeds the POR trigger level and will power down
into Reset mode when V
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a tem-
porary loss of power.
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A
dress. These pins have on-chip pull-down resistors.
WP: The Write Protect input pin inhibits all write op-
erations, when pulled HIGH. This pin has an on-chip
pull-down resistor.
FUNCTIONAL DESCRIPTION
The CAT24C256 supports the Inter-Integrated Circuit
(I
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data fl ow is controlled
by a Master device, which generates the serial clock
and all START and STOP conditions. The CAT24C256
acts as a Slave device. Master and Slave alternate as
either transmitter or receiver. Up to 8 devices may be
connected to the bus as determined by the device ad-
dress inputs A
Doc. No. MD-1104, Rev. G
2
0
C) Bus data transmission protocol, which defi nes a
, A
1
and A
2
: The Address pins accept the device ad-
0
, A
1
, and A
2
.
CC
drops below the POR
CC
4
I
The I
two wires are connected to the V
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake-up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when follow-
ing a Write command) or sends the Slave into standby
mode (when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The fi rst 4 bits of the Slave
address are set to 1010, for normal Read/Write opera-
tions (Figure 2). The next 3 bits, A
one of 8 possible Slave devices. The last bit, R/W,
specifi es whether a Read (1) or Write (0) operation is
to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9
also acknowledge the byte address and every data
byte presented in Write mode. In Read mode the Slave
shifts out a data byte, and then releases the SDA line
during the 9
the data, then the Slave continues transmitting. The
Master terminates the session by not acknowledging
the last data byte (NoACK) and by sending a STOP to
the Slave. Bus timing is illustrated in Figure 4.
2
C BUS PROTOCOL
2
C bus consists of two ‘wires’, SCL and SDA. The
th
clock cycle. If the Master acknowledges
th
clock cycle (Figure 3). The Slave will
Characteristics subject to change without notice
© 2008 SCILLC. All rights reserved
CC
2
, A
supply via pull-up
1
and A
0
, select