CYD04S72V-133BBC Cypress Semiconductor Corp, CYD04S72V-133BBC Datasheet - Page 6

• Manufacturer Part Number: CYD04S72V-133BBC
• Description: IC SRAM 4MBIT 133MHZ 484FBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYD04S72V-133BBC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 4M (64K x 72)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.42 V ~ 1.58 V, 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 3. Address Counter and Counter Mask Register Control Operation (Any Port)
Address Counter and Mask Register Operations
This section describes the features only apply to 4 Mbit and 9
Mbit devices, not to 18 Mbit device. Each port have a program-
mable burst address counter. The burst counter contains three
registers: a counter register, a mask register, and a mirror
register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only by
the Mask Load and Mask Reset operations, and by the MRST.
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more “0s” in the most significant bits define the masked region,
one or more “1s” in the least significant bits define the unmasked
region. Bit 0 may also be “0,” masking the least significant
counter bit and causing the counter to increment by two instead
of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset opera-
tions, and by the MRST.
Table 3
required input control signals. The MRST control signal is
Notes
Document Number : 38-06069 Rev. *K
15. X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
16. Counter operation and mask register operation is independent of chip enables.
17. The CYD04S72V has 16 address bits and a maximum address value of FFFF. The CYD09S72V has 17 address bits and a maximum address value of 1FFFF. The
CLK
X
CYD18S72V has 18 address bits and a maximum address value of 3FFFF.
summarizes the operation of these registers and the
MRST CNT/MSK CNTRST ADS CNTEN
H
H
H
H
H
H
H
H
H
L
X
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
X
L
L
X
X
H
H
X
H
L
L
L
L
H
H
H
X
X
X
X
L
L
L
Master Reset
Counter Reset
Counter Load
Counter Readback Read out counter internal value on address lines
Counter Increment Internally increment address counter value
Counter Hold
Mask Reset
Mask Load
Mask Readback
Reserved
[17]
Operation
asynchronous. All the other control signals in
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH transition
of that port’s clock signal. This will Read/Write one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array, and will loop
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to 0s. A counter-mask
register is used to control the counter wrap.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are
reset to “0.” All masked bits remain unchanged. A Mask
Reset followed by a Counter Reset will reset the counter
and mirror registers to 00000, as will master reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Reset address counter to all 0s and mask register
to all 1s
Reset counter unmasked portion to all 0s
Load counter with external address value presented
on address lines
Constantly hold the address value for multiple clock
cycles
Reset mask register to all 1s
Load mask register with value presented on the
address lines
Read out mask register value on address lines
Operation undefined
[15,16]
Description
CYD04S72V
CYD09S72V
CYD18S72V
Table 3
Page 6 of 26
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