CYD04S72V-133BBC Cypress Semiconductor Corp, CYD04S72V-133BBC Datasheet - Page 5

• Manufacturer Part Number: CYD04S72V-133BBC
• Description: IC SRAM 4MBIT 133MHZ 484FBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYD04S72V-133BBC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 4M (64K x 72)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.42 V ~ 1.58 V, 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Master Reset
The FLEx72 family devices undergo a complete reset by taking
the MRST input LOW. MRST input can switch asynchronously to
the clocks. MRST initializes the internal burst counters to zero,
and the counter mask registers to all ones (completely
unmasked). MRST also forces the mailbox interrupt (INT) flags
and the Counter Interrupt (CNTINT) flags HIGH. MRST must be
performed on the FLEx72 family devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports.
shows the interrupt operation for both ports using 18 Mbit device
as an example. The highest memory location, 3FFFF is the
mailbox for the right port and 3FFFE is the mailbox for the left
port. Table 2.shows that in order to set the INT
Table 2. Interrupt Operation Example
Document Number : 38-06069 Rev. *K
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
Notes
11. This family of Dual-Ports does not use V
12. CE is internal signal. CE = LOW if CE
13. OE is “Don’t Care” for mailbox operation.
14. At least one of BE0 or BE7 must be LOW.
V or 1.8 V. Please contact local Cypress FAE for more information.
and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
Left Port
Function
L
Flag
R
L
Flag
Flag
R
V
Flag
CORE
TMS
TDO
V
TCK
TDI
V
TTL
(continued)
SS
[11]
R/W
Right Port
X
X
H
L
L
0
= LOW and CE
CORE
, and these pins are internally NC. The next generation Dual-Port family, the FLEx72-E™, will use V
[1, 12, 13, 14]
CE
L
X
X
L
L
Left Port
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state
machine. State machine transitions occur on the rising edge of TCK.
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
registers.
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO
is normally three-stated except when captured data is shifted out of the JTAG TAP.
Ground Inputs.
Core Power Supply.
LVTTL Power Supply.
1
R
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK
flag, a write
Table 2
A
3FFFE
3FFFF
0L–17L
X
X
INT
operation by the left port to address 3FFFF will assert INT
At least one byte has to be active for a write to generate an
interrupt. A valid Read of the 3FFFF location by the right port will
reset INT
a read to reset the interrupt. When one port writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to is
asserted LOW.
The INT is reset when the owner (port) of the mailbox reads the
contents of the mailbox. The interrupt flag is set in a flow-thru
mode (i.e., it follows the clock edge of the writing port). Also, the
flag is reset in a flow-thru mode (i.e., it follows the clock edge of
the reading port)
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins should be left open.
X
X
H
L
L
R
HIGH. At least one byte has to be active in order for
R/W
Description
X
H
X
L
R
CE
X
X
L
L
Right Port
R
A
3FFFE
3FFFF
0R–17R
X
X
CYD04S72V
CYD09S72V
CYD18S72V
CORE
INT
Page 5 of 26
H
X
X
L
of 1.5
R
R
LOW.
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