CY7C1474BV25-167BGC Cypress Semiconductor Corp, CY7C1474BV25-167BGC Datasheet - Page 7

• Manufacturer Part Number: CY7C1474BV25-167BGC
• Description: IC SRAM 72MBIT 167MHZ 209FBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1474BV25-167BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (1M x 72)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 209-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 1. Pin Definitions
Document #: 001-15032 Rev. *D
A0
A1
A
BW
BW
BW
BW
BW
BW
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
DQ
DQP
MODE
TDO
TDI
Pin Name
1
2
3
s
a
b
c
d
e
f
g
h
X
JTAG Serial Input
Input Strap Pin
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
JTAG Serial
IO Type
Output
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
IO-
IO-
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the
CLK.
Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK. BW
DQ
DQP
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input Used to Advance the On-Chip Address Counter or Load a New Address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD must be driven
LOW to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Output Enable, Active LOW. Combined with the synchronous logic block inside the device to control
the direction of the IO pins. When LOW, the IO pins can behave as outputs. When deasserted HIGH,
IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has
been deselected.
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A
OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When
HIGH, DQ
the data portion of a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ
sequences, DQP
DQP
by BW
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE must not change states during operation. When
left floating MODE defaults HIGH, to an interleaved burst order.
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.
2
1
1
c
[18:0]
and CE
and DQP
f,
and CE
and CE
d
is controlled by BW
BW
g,
DQP
during the previous clock rise of the read cycle. The direction of the pins is controlled by
g
a
–DQ
controls DQ
2
3
3
to select/deselect the device.
h
to select/deselect the device.
to select/deselect the device.
c
, BW
is controlled by BW
h
a
are placed in a tri-state condition. The outputs are automatically tri-stated during
is controlled by BW
d
controls DQ
g
and DQP
d
, DQP
a
controls DQ
e
d
is controlled by BW
g,
h
and DQP
.
BW
a
, DQP
h
Pin Description
controls DQ
a
CY7C1472BV25, CY7C1474BV25
and DQP
d
b
, BW
is controlled by BW
e
controls DQ
e,
a
h
DQP
, BW
and DQP
f
b
is controlled by BW
controls DQ
e
h
b
and DQP
.
, DQP
CY7C1470BV25
c
b
is controlled by BW
and DQP
e,
BW
f,
DQP
f
[71:0]
controls DQ
b
, BW
g
. During write
is controlled
Page 7 of 29
c
controls
c
f
, and
and
[+] Feedback