CY7C1515V18-167BZXI Cypress Semiconductor Corp, CY7C1515V18-167BZXI Datasheet - Page 24

• Manufacturer Part Number: CY7C1515V18-167BZXI
• Description: IC SRAM 72MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1515V18-167BZXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 38-05363 Rev. *F
Parameter
t
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
23. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
24. This part has a voltage regulator internally; t
25. For D0 data signal on CY7C1526V18 device, t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
Cypress
operated and outputs data with the output timings of that frequency range.
initiated.
[25]
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
Parameter
V
K Clock and C Clock Cycle Time
Input Clock (K/K; C/C) HIGH
Input Clock (K/K; C/C) LOW
K Clock Rise to K Clock Rise and C
to C Rise (rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge)
Address Setup to K Clock Rise
Control Setup to K Clock Rise
(RPS, WPS)
Double Data Rate Control Setup to
Clock (K/K) Rise
(BWS
D
Address Hold after K Clock Rise
Control Hold after K Clock Rise
(RPS, WPS)
Double Data Rate Control Hold after
Clock (K/K) Rise
(BWS
D
DD
[X:0]
[X:0]
[22, 23]
(Typical) to the First Access
Hold after Clock (K/K) Rise
0
Setup to Clock (K/K) Rise
0
, BWS
, BWS
Description
POWER
1
1
SD
, BWS
, BWS
is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
is the time that the power must be supplied above V
2
2
, BWS
, BWS
3
3
)
)
[24]
1.32
1.32
1.49
Min Max Min Max Min Max Min Max Min Max
3.3
0.4
0.4
0.3
0.3
0.4
0.4
0.3
0.3
300 MHz
1
0
1.45
8.4
–
–
–
–
–
–
–
–
–
–
–
3.6
1.4
1.4
1.6
0.4
0.4
0.3
0.3
0.4
0.4
0.3
0.3
278 MHz
1
0
1.55
CY7C1513V18, CY7C1515V18
CY7C1511V18, CY7C1526V18
8.4
–
–
–
–
–
–
–
–
–
–
–
DD
minimum initially before a read or write operation can be
0.35
0.35
0.35
0.35
1.6
1.6
1.8
4.0
0.5
0.5
0.5
0.5
250 MHz
1
0
8.4
1.8
–
–
–
–
–
–
–
–
–
–
–
5.0
2.0
2.0
2.2
0.6
0.6
0.4
0.4
0.6
0.6
0.4
0.4
200 MHz
1
0
8.4
2.2
–
–
–
–
–
–
–
–
–
–
–
6.0
2.4
2.4
2.7
0.7
0.7
0.5
0.5
0.7
0.7
0.5
0.5
167 MHz
1
0
Page 24 of 32
8.4
2.7
–
–
–
–
–
–
–
–
–
–
–
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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