CY7C1520AV18-200BZXI Cypress Semiconductor Corp, CY7C1520AV18-200BZXI Datasheet

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... C and C if provided the rising edge of K and and C are not provided. On CY7C1518AV18 and CY7C1520AV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1518AV18 and two 36-bit words in the case of CY7C1520AV18 sequentially into or out of the device ...

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... Logic Block Diagram (CY7C1518AV18) Burst A0 Logic (21:0) A Address (21:1) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1520AV18) Burst A0 Logic (20:0) A Address (20:1) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 001-06982 Rev. *F ...

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... Contents 72-Mbit DDR-II SRAM Two-Word Burst Architecture .... 1 Features ............................................................................. 1 Configurations .................................................................. 1 Functional Description ..................................................... 1 Selection Guide ................................................................ 1 Logic Block Diagram (CY7C1518AV18) .......................... 2 Logic Block Diagram (CY7C1520AV18) .......................... 2 Pin Configuration 4 165-Ball FBGA (15 × 17 × 1.4 mm) Pinout .................. 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 7 Read Operations ......................................................... 7 Write Operations ......................................................... 7 Byte Write Operations ................................................. 7 Single Clock Mode ...................................................... 7 DDR Operation ...

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... Pin Configuration The following table shows the pin configuration for parts, CY7C1518AV18 and CY7C1520AV18 DQ9 DQ10 DQ11 F NC DQ12 DQ13 H DOFF V V REF DDQ DQ14 L NC DQ15 DQ16 DQ17 R TDO TCK NC/144M DQ27 DQ18 DQ28 D NC DQ29 DQ19 DQ20 F NC DQ30 ...

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... CY7C1518AV18 – the input to the burst counter. These are incremented in a linear fashion internally. 22 address inputs are needed to access the entire memory array. CY7C1520AV18 – the input to the burst counter. These are incremented in a linear fashion internally. 21 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected ...

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... Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC REF Reference measurement points. V Power Supply Power Supply Inputs to the Core of the Device Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-06982 Rev. *F CY7C1518AV18 CY7C1520AV18 Pin Description Page [+] Feedback ...

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... Functional Overview The CY7C1518AV18, and CY7C1520AV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and a half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to V the device behaves in DDR-I mode with a read latency of SS one clock cycle ...

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... DDR-I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRII™/DDRII. Figure 1. Application Example R = 250ohms SRAM#1 ZQ CQ/CQ# LD# R/ CY7C1518AV18 CY7C1520AV18 R = 250ohms SRAM CQ/CQ# A LD# R/ Page [+] Feedback ...

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... X = “Do not Care,” Logic HIGH Logic LOW, ↑ represents rising edge. 3. Device powers up deselected with the outputs in a tristate condition CY7C1518AV18 and CY7C1520AV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses sequence in the burst. ...

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... Write Cycle Descriptions The following table represents the write cycle description for the part, CY7C1520AV18. BWS BWS BWS BWS L– – L– – L– – L– – L– – L– – Document Number: 001-06982 Rev Comments – During the data portion of a write sequence, all four bytes (D the device. L– ...

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... TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. CY7C1518AV18 CY7C1520AV18 TAP Controller Block Diagram on ) when SS on page 17 shows the order in which ...

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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-06982 Rev. *F CY7C1518AV18 CY7C1520AV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...

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... Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06982 Rev. *F [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1518AV18 CY7C1520AV18 1 SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...

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... Boundary Scan Register TAP Controller Test Conditions = −2 −100 μ 2 100 μ GND ≤ V ≤ − /2), Undershoot: V (AC) > 1.5 V (Pulse width less than t CYC IL CY7C1518AV18 CY7C1520AV18 Selection TDO Circuitry Min Max Unit 1.4 V 1.6 V 0.4 V 0 –0.3 0. μA –5 5 Electrical Characteristics Table ...

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... Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-06982 Rev. *F Description [14] Figure 2. TAP Timing and Test Conditions 0 Ω TMSH t TMSS t TDIS t TDIH t TDOV / ns CY7C1518AV18 CY7C1520AV18 Min Max Unit 50 20 MHz ALL INPUT PULSES 0 TCYC t TDOX Page ...

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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-06982 Rev. *F Value CY7C1520AV18 000 000 11010100010100100 00000110100 00000110100 1 Description CY7C1518AV18 CY7C1520AV18 Description Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. 1 Indicates the presence register. Bit Size ...

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... Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D 11B 70 3C 11C 10B 73 3E 11A 74 2D 10A CY7C1518AV18 CY7C1520AV18 Bit # Bump 100 2P 101 1P 102 3R 103 4R 104 4P 105 5P 106 5N 107 5R 108 Internal Page [+] Feedback ...

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... DLL may lock onto an incorrect frequency, causing unstable . SRAM behavior. To avoid this, provide1024 cycles stable clock REF to relock to the desired clock frequency. Figure 3. Power-up Waveforms > 1024 Stable clock Stable DDQ Stable (< +/- 0.1V DC per 50ns ) / DDQ Fix High (or tie to V DDQ ) CY7C1518AV18 CY7C1520AV18 . KC Var Start Normal Operation Page [+] Feedback ...

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... Typical value = 0.75 V (min) within 200 ms. During this time V < V and /2)/(RQ/5) for values of 175 Ω < RQ < 350 Ω (max whichever is smaller REF DDQ CY7C1518AV18 CY7C1520AV18 Test Description Typ Max* Unit Conditions Logical 25° C 320 368 single-bit upsets Logical 25° ...

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... 1/t , Inputs 278 MHz (x18) MAX CYC Static (x36) 250 MHz (x18) (x36) 200 MHz (x18) (x36) 167 MHz (x18) (x36) Test Conditions CY7C1518AV18 CY7C1520AV18 Min Typ Max Unit 940 mA 1080 860 985 800 900 700 735 650 650 400 mA 400 ...

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... REF V 0. Ω REF OUTPUT Device 0. Under ZQ Test RQ = 250 Ω INCLUDING JIG AND (b) SCOPE / I and load capacitance shown in ( CY7C1518AV18 CY7C1520AV18 Max Unit = 1.5 V 5.5 pF DDQ 8 165 FBGA Unit Package 16.3 ° 2.1 ° [20] ALL INPUT PULSES 1.25 V 0.75 V Slew Rate = 2 V/ 250 Ω ...

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... BWS ) 2 3 0.3 – 0.3 – is the time that the power is supplied above V min initially before a read or write operation can be initiated. DD CY7C1518AV18 CY7C1520AV18 250 MHz 200 MHz 167 MHz Unit 1 – 1 – 1 – ms 4.0 8.4 5.0 8.4 6 ...

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... An input jitter of 200 ps (t KHKH Waveforms. Transition is measured ±100 mV from steady-state voltage. AC Test Loads and and t less than t . CLZ CHZ CO CY7C1518AV18 CY7C1520AV18 250 MHz 200 MHz 167 MHz Unit – 0.45 – 0.45 – 0.50 ns – ...

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... In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-06982 Rev. *F NOP NOP WRITE WRITE Q00 Q01 Q10 Q11 D20 t CQDOH t CHZ t DOH t CQD CCQO t CQOH t CCQO CY7C1518AV18 CY7C1520AV18 [26, 27, 28] READ D21 D30 D31 Q40 Q41 t KHKH t CYC t CQH t CQHCQH DON’T CARE UNDEFINED Page [+] Feedback ...

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... Table 1. Key Features and Ordering Information Speed (MHz) Ordering Code 250 CY7C1518AV18-250BZC CY7C1520AV18-250BZC CY7C1520AV18-250BZXC CY7C1518AV18-250BZI CY7C1518AV18-250BZXI 200 CY7C1520AV18-200BZC CY7C1520AV18-200BZI CY7C1520AV18-200BZXI 167 CY7C1518AV18-167BZC Ordering Code Definitions 15XX A V18 - XXX BZ( Document Number: 001-06982 Rev. *F and refer to the product summary page at http://www.cypress.com/products. Package Diagram Package Type 51-85195 165-Ball FBGA (15 × ...

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... SRAM static random access memory TCK test clock TDI test data in TDO test data out TMS test mode select Document Number: 001-06982 Rev. *F Figure 6. 165-Ball FBGA (15 × 17 × 1.4 mm 0.15(4X) CY7C1518AV18 CY7C1520AV18 BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. +0.14 Ø0.50 (165X) -0. ...

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... Document History Page Document Title: CY7C1518AV18/CY7C1520AV18, 72-Mbit DDR-II SRAM Two-Word Burst Architecture Document Number: 001-06982 Orig. of Submission Revision ECN Change ** 433241 NXR *A 462002 NXR *B 503690 VKN *C 1523443 VKN/AESA *D 2509299 VKN/AESA *E 2880098 VKN/AESA *F 2957481 VKN Document Number: 001-06982 Rev. *F Description of Change Date ...

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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06982 Rev. *F All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised August 11, 2010 CY7C1518AV18 CY7C1520AV18 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | ...