CY7C028-15AI Cypress Semiconductor Corp, CY7C028-15AI Datasheet
CY7C028-15AI
Specifications of CY7C028-15AI
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CY7C028-15AI Summary of contents
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... True dual-ported memory cells which allow simultaneous access of the same memory location ■ 32K x 16 organization (CY7C027) ■ 64K x 16 organization (CY7C028) ■ 32K x 18 organization (CY7C037) ■ 64K x 18 organization (CY7C038) ■ 0.35 micron CMOS for optimum speed and power [1] ■ ...
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... An automatic power down feature is controlled independently on each port by the chip enable pins. The CY7C027/028 and CY7C037/038 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Figure 1. 100-Pin TQFP (Top View CY7C028 (64K x 16) CY7C027 (32K x 16 CY7C027/028 CY7C037/038 80 ...
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Pin Configurations (continued) 100 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [7] A15L 7 LBL 8 UBL 9 CE0L 10 CE1L 11 SEML 12 R/WL 13 OEL 14 VCC 15 GND 16 ...
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Pin Definitions Left Port Right Port R/W R –A A –A 0L 15L 0R 15R I/O –I/O I/O –I/O 0L 17L 0R 17R ...
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... MAX Notes 8. The voltage on any input or I/O pin cannot exceed the power pin during power up. 9. Pulse width < 20 ns. 10. Industrial parts are available in CY7C028 and CY7C038 only. 11 1/t = All inputs cycling 1/t (except output enable means no address or control lines change. This applies only to inputs at CMOS ...
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Capacitance [12] Parameter Description C Input Capacitance IN C Output Capacitance OUT 893Ω OUTPUT 347Ω (a) Normal Load (Load 1) AC Test Loads (Applicable to -12 only 50Ω R ...
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Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [15 LOW to Data Valid ACE t OE LOW to ...
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Switching Characteristics Over the Operating Range Parameter Description [20] INTERRUPT TIMING t INT Set Time INS t INT Reset Time INR SEMAPHORE TIMING t SEM Flag Update Pulse (OE or SEM) SOP t SEM Flag Write to Read Time SWRD ...
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Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT ...
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Switching Waveforms (continued) Figure 7. Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [32,33 R/W NOTE 35 DATA OUT DATA IN Figure 8. Write Cycle No Controlled Timing ADDRESS [32,33 R/W ...
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Switching Waveforms (continued) Figure 9. Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Figure 10. Timing Diagram of Semaphore Contention A – R/W L ...
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Switching Waveforms (continued) Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 41. CE ...
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Switching Waveforms (continued) Figure 13. Busy Timing Diagram No.1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Figure 14. Busy Timing Diagram ...
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... Switching Waveforms (continued) Left Side Sets INT : R ADDRESS WRITE 7FFF (FFFF for CY7C028/38 R/W L INT R [44] t INS Right Side Clears INT : R ADDRESS R INT R Right Side Sets INT : L ADDRESS WRITE 7FFE (FFFE for CY7C028/38 R/W R INT L [44] t INS Left Side Clears INT ...
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... CY7C027/37, FFFF for the CY7C028/38) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027/37, FFFE for the CY7C028/38) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox ...
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... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes 23. A and A , FFFF/FFFE for the CY7C028/038. 0L–15L 0R–15R 24. If BUSY = L, then no change. R 25. If BUSY = L, then no change. ...
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... CY7C027-12AC 15 CY7C027-15AC CY7C027-15AXI 20 CY7C027-20AC CY7C027-20AXC 64K x16 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C028-12AC CY7C028-12AXC 15 CY7C028-15AC CY7C028-15AXC CY7C028-15AI CY7C028-15AXI 20 CY7C028-20AC CY7C028-20AI 32K x18 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C037-12AC 15 CY7C037-15AC 20 CY7C037-20AC 64K x18 Asynchronous Dual-Port SRAM Speed (ns) ...
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Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06042 Rev. *D CY7C027/028 CY7C037/038 51-85048-*C Page [+] Feedback ...
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... Power up requirements added to Maximum Ratings Information 6/23/04 Removed cross information from features section See ECN Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C027-20AXC, CY7C028-12AXC, CY7C028-15AXC, CY7C028-15AI, CY7C028-15AXI 12/17/08 Added CY7C027-15AXI in the Ordering information table PSoC Solutions General psoc.cypress.com Low Power/Low Voltage clocks ...