CY7C1370D-167AXC Cypress Semiconductor Corp, CY7C1370D-167AXC Datasheet - Page 14

• Manufacturer Part Number: CY7C1370D-167AXC
• Description: IC SRAM 18MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1370D-167AXC

• Memory Size: 18M (512K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.4 ns
• Maximum Clock Frequency: 167 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 275 mA
• Organization: 128 K x 16
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 1M X 18 / 512K X 36
• Clock Frequency: 167MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2135; CY7C1370D-167AXC

the TAP controller, it will directly control the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to drive
the output bus. When LOW, this bit will place the output bus into
a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
Document Number: 38-05555 Rev. *K
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
Notes
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
9. t
10. Test conditions are specified using the load in TAP AC test Conditions. t
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
Test M ode Select
Test Data-Out
Test Data-In
Test Clock
[9, 10]
(TDO)
(TM S)
(TCK )
(TDI)
1
Description
t TM SS
t TDIS
2
t TM SH
t TDIH
t TH
DON’T CA RE
R
/t
F
= 1 ns.
t
TL
3
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is preset
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t CY C
UNDEFINED
4
t TDOX
t TDOV
CY7C1370D, CY7C1372D
Min
50
20
20
0
5
5
5
5
5
5
5
Max
20
10
6
Page 14 of 29
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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