CY7C024AV-20AXC Cypress Semiconductor Corp, CY7C024AV-20AXC Datasheet - Page 12

• Manufacturer Part Number: CY7C024AV-20AXC
• Description: IC SRAM 64KBIT 20NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C024AV-20AXC

• Memory Size: 64K (4K x 16)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 20 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 175 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2092; CY7C024AV-20AXC

Switching Waveforms
Document #: 38-06052 Rev. *M
Notes
CE
34. R/W or CE must be HIGH during all address transitions.
35. A write occurs during the overlap (t
36. t
37. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
38. To access RAM, CE = V
39. To access upper byte, CE = V
40. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested.
41. During this period, the IO pins are in the output state, and input signals must not be applied.
42. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
data to be placed on the bus for the required t
be as short as the specified t
To access lower byte, CE = V
[38, 39]
HA
[38, 39]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
R/W
R/W
OE
IL
, SEM = V
PWE
Figure 8. Write Cycle No. 1: R/W Controlled Timing
IL
IL
Figure 9. Write Cycle No. 2: CE Controlled Timing
t
t
, LB = V
, UB = V
SA
SA
NOTE 41
.
(continued)
SCE
IH
.
IL
or t
IL
, SEM = V
, SEM = V
PWE
SD
) of a LOW CE or SEM and a LOW UB or LB.
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
t
HZWE
IH
IH
.
.
[40]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[37]
t
t
SD
SD
CY7C024AV/024BV/025AV/026AV
PWE
or (t
[34, 35, 36, 42]
[34, 35, 36, 37]
t
t
HA
HA
CY7C0241AV/0251AV/036AV
HZWE
t
t
HD
HD
+ t
t
LZWE
SD
) to enable the IO drivers to turn off and
t
HZOE
[40]
NOTE 41
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