CY7C1360C-166AXC Cypress Semiconductor Corp, CY7C1360C-166AXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1360C-166AXC
• Description: IC SRAM 9MBIT 166MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1360C-166AXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.5 ns
• Maximum Clock Frequency: 166 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Density: 9Mb
• Access Time (max): 3.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Memory Configuration: 512K X 18 / 256K X 36
• Clock Frequency: 166MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2124; CY7C1360C-166AXC

Document Number: 38-05540 Rev. *K
Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250 MHz device).
The CY7C1360C/CY7C1362C supports secondary cache in
systems using either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that use a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the processor address
strobe (ADSP) or the controller address strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous chip selects (CE
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE
HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE
(A) is stored into the address advancement logic and the
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
TDO
TDI
TMS
TCK
NC
NC (18,36,
72, 144, 288,
576, 1G)
Note
4. CE
Name
1
1
3
is HIGH. The address presented to the address inputs
, CE
is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.
2
, CE
JTAG serial input
JTAG serial input
synchronous
synchronous
synchronous
JTAG serial
3
[4]
output
JTAG-
clock
are all asserted active, and (3) the write
I/O
(continued)
–
–
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being used, this pin should be disconnected. This pin is not available on TQFP
packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being used, this pin can be disconnected or connected to V
TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being used, this pin can be disconnected or connected to V
TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be
connected to V
No connects. Not internally connected to the die
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
288M, 576M, and 1G densities.
X
) inputs. A global write
1
, CE
2
, CE
CO
SS
3
) is 2.8 ns
[4]
. This pin is not available on TQFP packages.
) and an
1
is
the output registers. At the rising edge of the next clock, the
data is allowed to propagate through the output register and
on the data bus within 2.8 ns (250 MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tristated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported. After the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output tristates immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW and
(2) CE
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The write signals (GW, BWE, and BW
ADV inputs are ignored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BW
signals. The CY7C1360C/CY7C1362C provides byte write
capability that is described in the Write Cycle Descriptions
table. Asserting the byte write enable input (BWE) with the
selected byte write (BW
the desired bytes. Bytes not selected during a byte write
operation remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Because the CY7C1360C/CY7C1362C is a common I/O
device, the output enable (OE) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so tristates
the output drivers. As a safety precaution, DQs are
automatically tristated whenever a Write cycle is detected,
regardless of the state of OE.
1
, CE
Description
2
, CE
3
[4]
CY7C1360C, CY7C1362C
are all asserted active. The address
X
) input, will selectively write to only
DD
DD
. This pin is not available on
. This pin is not available on
Page 9 of 34
X
) and
X
[+] Feedback