CY7C1360C-166AXC Cypress Semiconductor Corp, CY7C1360C-166AXC Datasheet - Page 18

• Manufacturer Part Number: CY7C1360C-166AXC
• Description: IC SRAM 9MBIT 166MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1360C-166AXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.5 ns
• Maximum Clock Frequency: 166 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Density: 9Mb
• Access Time (max): 3.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Memory Configuration: 512K X 18 / 256K X 36
• Clock Frequency: 166MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2124; CY7C1360C-166AXC

Identification Register Definitions
Scan Register Sizes
Identification Codes
Document Number: 38-05540 Rev. *K
Revision number (31:29)
Device depth (28:24)
Device width (23:18) 119-BGA
Device width (23:18) 165- FBGA
Cypress device ID (17:12)
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
Instruction
Bypass
ID
Boundary scan order (119-ball BGA package)
Boundary scan order (165-ball FBGA package)
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Note
17. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device.
Instruction
Instruction Field
Register Name
[17]
Code
000
001
010
011
100
101
110
111
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high Z state.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
00000110100
CY7C1360C
(256KX36)
101000
000000
100110
01011
000
1
00000110100
CY7C1362C
(512KX18)
Bit Size (× 36)
101000
000000
010110
01011
000
1
32
71
71
3
1
Description
Describes the version number
Reserved for internal use
Defines width and density
Allows unique identification of SRAM vendor
Defines memory type and architecture
Defines memory type and architecture
Indicates the presence of an ID register
CY7C1360C, CY7C1362C
Description
Bit Size (× 18)
32
71
71
3
1
Page 18 of 34
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