CY7C1363C-133AXC Cypress Semiconductor Corp, CY7C1363C-133AXC Datasheet - Page 24

• Manufacturer Part Number: CY7C1363C-133AXC
• Description: IC SRAM 9MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1363C-133AXC

• Memory Size: 9M (512K x 18)
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Memory Configuration: 512K X 18 / 256K X 36
• Clock Frequency: 133MHz
• Access Time: 6.5ns
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Density: 9Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 250mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Number Of Words: 512K
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2131; CY7C1363C-133AXC

Timing Diagrams
Note
Document Number: 38-05541 Rev. *J
25. On this diagram, when CE is LOW: CE
GW, BWE,BW
Data Out (Q)
ADDRESS
CLK
ADSP
ADSC
ADV
OE
X
CE
High-Z
t ADS
t AS
t CES
A1
t ADH
t CLZ
t
t AH
t CEH
CH
t OEV
t CDV
t CYC
Single READ
t
t CL
WES
1
Q(A1)
is LOW, CE
t
WEH
t OEHZ
t ADS
A2
2
t ADH
is HIGH and CE
t OELZ
Figure 6. Read Cycle Timing
t
ADVS
Q(A2)
t
t DOH
ADVH
t CDV
3
is LOW. When CE is HIGH: CE
Q(A2 + 1)
DON’T CARE
Q(A2 + 2)
ADV suspends burst
UNDEFINED
[25]
BURST
READ
1
is HIGH or CE
Q(A2 + 3)
CY7C1361C/CY7C1363C
2
is LOW or CE
Q(A2)
Burst wraps around
to its initial state
3
Q(A2 + 1)
is HIGH.
Deselect Cycle
Page 24 of 34
Q(A2 + 2)
t CHZ
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