CY62158ELL-45ZSXI Cypress Semiconductor Corp, CY62158ELL-45ZSXI Datasheet

IC SRAM 8MBIT 45NS 44-TSOP

CY62158ELL-45ZSXI

Manufacturer Part Number
CY62158ELL-45ZSXI
Description
IC SRAM 8MBIT 45NS 44-TSOP
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr

Specifications of CY62158ELL-45ZSXI

Memory Size
8M (1M x 8)
Package / Case
44-TSOP II
Format - Memory
RAM
Memory Type
SRAM
Speed
45ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Access Time
45 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Current
25 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
5 V
Memory Configuration
1M X 8
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
TSOP
No. Of Pins
44
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
8-bit (1M x 8) Static RAM
Features
Functional Description
The CY62158E MoBL
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
Cypress Semiconductor Corporation
Document #: 38-05684 Rev. *G
Very high speed: 45 ns
Ultra low active power
Ultra low standby power
Easy memory expansion with CE
Automatic power down when deselected
CMOS for optimum speed and power
Offered in Pb-free 44-Pin TSOP II package
Logic Block Diagram
Wide voltage range: 4.5V – 5.5V
Typical active current:1.8 mA at f = 1 MHz
Typical active current: 18 mA at f = f
Typical standby current: 2 A
Maximum standby current: 8 A
is a high performance CMOS static RAM
CE 1
CE 2
WE
OE
1
, CE
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 10
A 11
A 12
max
2
and OE features
198 Champion Court
COLUMN DECODER
DATA IN DRIVERS
1024K x 8
ARRAY
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption significantly when deselected (CE
CE
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O
on the address pins (A
To read from the device, take Chip Enables (CE
HIGH) and OE LOW while forcing the WE HIGH. Under these
conditions, the contents of the memory location specified by the
address pins appear on the I/O pins.
The eight input and output pins (I/O
a high impedance state when the device is deselected (CE
HIGH or CE
write operation is in progress (CE
LOW). See the
of read and write modes.
For best practice recommendations, refer to the Cypress
application note
2
POWER
DOWN
LOW).
8-Mbit (1M x 8) Static RAM
0
through I/O
San Jose
2
LOW), the outputs are disabled (OE HIGH), or a
Truth Table
AN1064, SRAM System Guidelines
,
7
) is then written into the location specified
0
CA 95134-1709
through A
on page 9 for a complete description
CY62158E MoBL
1
19
LOW and CE
Revised December 28, 2010
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
).
through I/O
IO 0
IO 1
IO 2
IO 3
IO 4
IO 5
IO 6
IO 7
0
1
2
3
4
5
6
7
1
1
2
7
LOW and CE
LOW and CE
) are placed in
HIGH and WE
408-943-2600
) in portable
1
HIGH or
2
2
1
[+] Feedback

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CY62158ELL-45ZSXI Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-05684 Rev. *G 8-Mbit ( Static RAM is ideal for providing More Battery Life™ (MoBL applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces ...

Page 2

Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... ...

Page 3

... Product Portfolio Product V Range (V) CC Min Typ CY62158ELL 4.5 5.0 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V Document #: 38-05684 Rev. *G Figure 1. 44-Pin TSOP II (Top View) ...

Page 4

... CMOS levels to meet the Document #: 38-05684 Rev Input Voltage Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA Operating Range + 0.5V CC(max) Device + 0.5V CY62158ELL CC(max) Test Conditions I = – 2 4. 4.5V to 5.5V CC GND < ...

Page 5

OUTPUT R2 100 pF INCLUDING JIG AND SCOPE Parameters Data Retention Characteristics Over the Operating Range Parameter Description V V for Data Retention DR CC [8] I Data Retention Current CCDR ...

Page 6

... HZOE HZCE HZWE 14. The internal write time of the memory is defined by the overlap of WE, CE can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05684 Rev. *G Description ...

Page 7

Switching Waveforms Figure 4 shows address transition controlled read cycle waveforms. ADDRESS PREVIOUS DATA VALID DATA OUT Figure 5 shows OE controlled read cycle waveforms. ADDRESS ACE OE t LZOE HIGH IMPEDANCE DATA OUT t ...

Page 8

... DATA I/O Notes 18. The internal write time of the memory is defined by the overlap of WE, CE can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 19. Data I/O is high impedance 20 goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state ...

Page 9

Switching Waveforms (continued) Figure 8 shows WE controlled, OE LOW write cycle waveforms. ADDRESS DATA I/O NOTE 21 t HZWE Truth Table [22 ...

Page 10

... Ordering Information Speed (ns) Ordering Code 45 CY62158ELL-45ZSXI Contact your local Cypress sales representative for availability of this part. Ordering Code Definitions 621 -xx xxx CY 8 Document #: 38-05684 Rev. *G Package Package Type Diagram 51-85087 44-Pin TSOP II (Pb-free) I Temperature Grade Industrial Package Type: ZSX = VFBGA (Pb-free) ...

Page 11

Package Diagrams 22 23 TOP VIEW 0.400(0.016) 0.800 BSC 0.300 (0.012) (0.0315) 18.517 (0.729) 18.313 (0.721) DIMENSION IN MM (INCH) MAX MIN. Document #: 38-05684 Rev. *G Figure 9. 44-Pin TSOP II, 51-85087 PIN 1 I. BASE PLANE ...

Page 12

Document History Page  Document Title: CY62158E MoBL 8-Mbit ( Static RAM Document Number: 38-05684 REV. ECN NO. Issue Date ** 270350 See ECN *A 291271 See ECN *B 1462592 See ECN VKN/AESA Converted from preliminary to final ...

Page 13

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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