CY62157EV30LL-45BVXI Cypress Semiconductor Corp, CY62157EV30LL-45BVXI Datasheet
CY62157EV30LL-45BVXI
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CY62157EV30LL-45BVXI
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CY62157EV30LL-45BVXI Summary of contents
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... Power Down Circuit Cypress Semiconductor Corporation Document #: 38-05445 Rev Mbit (512K x 16) Static RAM Functional Description The CY62157EV30 is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life ...
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Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ...
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... Product Portfolio Product Range Min CY62157EV30LL Industrial/ 2.2 Auto-A Auto-E 2.2 Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured pins are not connected on the die. 3. The 44-TSOP II package has only one chip enable (CE) pin. ...
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... BLE) and BYTE (48 TSOP I only) need to be tied to CMOS levels to meet the left floating. Document #: 38-05445 Rev. *H Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage .......................................... > 2001V (MIL-STD-883, Method 3015) Latch Up Current ................................................... > 200 mA Operating Range Device + 0.3V) CY62157EV30LL CCmax + 0.3V) CCmax + 0.3V) CC max 45 ns (Ind’l/Auto-A) Test Conditions Min Typ 2.0 > 2.70V 2 ...
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Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description C Input capacitance Output capacitance OUT Thermal Resistance Tested initially and after any design or process changes ...
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Data Retention Characteristics Over the Operating Range Parameter Description V V for data retention Data retention current CCDR CE [11] t Chip deselect to data CDR retention time [12] t Operation recovery time R Data Retention ...
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... If both byte enables are toggled together, this value is 10 ns. 19. The internal write time of the memory is defined by the overlap of WE write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write ...
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Switching Waveforms Figure 6 shows Address Transition Controlled read cycle waveforms. ADDRESS DATA OUT PREVIOUS DATA VALID Figure 7 shows OE Controlled read cycle waveforms. ADDRESS BHE/BLE t LZBE OE HIGH IMPEDANCE DATA OUT t ...
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... HZOE Notes 23. The internal write time of the memory is defined by the overlap of WE write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 24. Data I/O is high impedance ...
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Switching Waveforms (continued) Figure 10 shows WE Controlled, OE LOW write cycle waveforms. ADDRESS BHE/BLE NOTE 28 DATA I/O t HZWE Figure 11 shows BHE/BLE Controlled, OE LOW write cycle waveforms. ADDRESS CE ...
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Truth Table BHE 1 2 [29 [29 [29] [29 ...
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... Ordering Information Speed (ns) Ordering Code 45 CY62157EV30LL-45BVI CY62157EV30LL-45BVXI CY62157EV30LL-45ZSXI CY62157EV30LL-45ZXI CY62157EV30LL-45BVXA CY62157EV30LL-45ZSXA CY62157EV30LL-45ZXA 55 CY62157EV30LL-55ZSXE CY62157EV30LL-55ZXE Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions E V30 LL xx xxx CY 621 5 7 Document #: 38-05445 Rev. *H Package Package Type Diagram 51-85150 48-ball very fine pitch ball grid array ...
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Package Diagrams Figure 12. 48-Pin VFBGA ( mm), 51-85150 Document #: 38-05445 Rev. *H ® CY62157EV30 MoBL 51-85150-*E Page [+] Feedback ...
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Package Diagrams (continued TOP VIEW 0.400(0.016) 0.800 BSC 0.300 (0.012) (0.0315) 18.517 (0.729) 18.313 (0.721) DIMENSION IN MM (INCH) MAX MIN. Document #: 38-05445 Rev. *H Figure 13. 44-Pin TSOP II, 51-85087 PIN 1 I. BASE ...
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Package Diagrams (continued) Figure 14. 48-Pin TSOP 1.0 mm), 51-85183 Document #: 38-05445 Rev. *H ® CY62157EV30 MoBL 51-85183-*B Page [+] Feedback ...
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Document History Page Document Title: CY62157EV30 MoBL Document Number: 38-05445 Orig. of Submission Rev. ECN No. Change Date ** 202940 AJU See ECN *A 291272 SYT See ECN *B 444306 NXR See ECN *C 467052 NXR See ECN *D 925501 ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...