CY7C1041D-10VXI Cypress Semiconductor Corp, CY7C1041D-10VXI Datasheet - Page 4

• Manufacturer Part Number: CY7C1041D-10VXI
• Description: IC SRAM 4MBIT 10NS 44SOJ
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C1041D-10VXI

• Memory Size: 4M (256K x 16)
• Package / Case: 44-SOJ
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 10 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 90 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Density: 4Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 18b
• Package Type: SOJ
• Operating Temp Range: -40C to 85C
• Supply Current: 90mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 256K
• Memory Configuration: 256K X 16
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOJ
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1975-5; CY7C1041D-10VXI

Document #: 38-05472 Rev. *E
Switching Characteristics
Data Retention Characteristics
Data Retention Waveform
Switching Waveforms
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
V
I
I
t
t
Read Cycle No. 1
Notes:
10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
12. Full device operation requires linear V
13. No input may exceed V
14. Device is continuously selected. OE, CE, BHE, and/or BHE = V
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
CCDR
CCDR
CDR
R
DR
[12]
DATA OUT
Parameter
ADDRESS
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the
Write.
Parameter
[4]
V
CE
CC
[10, 11]
V
Data Retention Current
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
[13, 14]
CC
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write
CC
for Data Retention
PREVIOUS DATA VALID
+ 0.5V
Description
CC
[6]
Description
ramp from V
Over the Operating Range(continued)
[9]
[8, 9]
Over the Operating Range
t
OHA
t
CDR
4.5V
DR
to V
t
CC(min.)
AA
IL
.
V
CE > V
V
> 50 s or stable at V
CC
IN
DATA RETENTION MODE
> V
= V
CC
CC
DR
– 0.3V,
– 0.3V or V
t
RC
= 2.0V,
V
DR
Min.
Conditions
-10 (Industrial)
10
7
7
7
0
0
6
0
3
7
> 2V
CC(min.)
HZWE
IN
< 0.3V
> 50 s
and t
[13]
Max.
5
SD
.
Auto
Ind’l
-12 (Automotive)
DATA VALID
Min.
4.5V
12
10
10
10
10
0
0
7
0
3
t
R
Min.
2.0
t
RC
0
CY7C1041D
Max.
6
Max.
10
15
Page 4 of 11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
mA
mA
ns
ns
V
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