CY7C1011DV33-10ZSXI Cypress Semiconductor Corp, CY7C1011DV33-10ZSXI Datasheet

IC SRAM 2MBIT 10NS 44TSOP

CY7C1011DV33-10ZSXI

Manufacturer Part Number
CY7C1011DV33-10ZSXI
Description
IC SRAM 2MBIT 10NS 44TSOP
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr
Datasheet

Specifications of CY7C1011DV33-10ZSXI

Memory Size
2M (128K x 16)
Package / Case
44-TSOP II
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Speed
10ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Access Time
10 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
90 mA
Organization
128 K x 16
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
3.3 V
Memory Configuration
128K X 16
Supply Voltage Range
3V To 3.6V
Memory Case Style
TSOP
No. Of Pins
44
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Density
2Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
17b
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Supply Current
90mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Word Size
16b
Number Of Words
128K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1962
CY7C1011DV33-10ZSXI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1011DV33-10ZSXI
Manufacturer:
RENESAS
Quantity:
1 056
Company:
Part Number:
CY7C1011DV33-10ZSXI
Quantity:
4 400
Part Number:
CY7C1011DV33-10ZSXIT
0
Cypress Semiconductor Corporation
Document Number: 38-05609 Rev. *E
2-Mbit (128 K × 16) Static RAM
Features
Logic Block Diagram
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at
Pin-and function-compatible with CY7C1011CV33
High speed
Low active power
Low CMOS standby power
Data Retention at 2.0 V
Automatic power-down when deselected
Independent control of upper and lower bits
Easy memory expansion with CE and OE features
Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA
t
I
I
AA
CC
SB2
= 10 ns
= 90 mA @ 10 ns (Industrial)
= 10 mA
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
198 Champion Court
INPUT BUFFER
DECODER
COLUMN
128K X 16
2-Mbit (128 K × 16) Static RAM
Functional Description
The CY7C1011DV33
RAM organized as 128 K words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011DV33 is available in standard Pb-free 44-pin
TSOP II with center power and ground pinout, as well as
48-ball very fine-pitch ball grid array (VFBGA) packages.
16
San Jose
). If Byte High Enable (BHE) is LOW, then data
8
through I/O
,
[1]
0
CA 95134-1709
is a high-performance CMOS Static
to I/O
I/O
I/O
0
0
8
–I/O
–I/O
through I/O
BHE
WE
CE
OE
BLE
7
. If Byte High Enable (BHE) is
15
0
7
15
) is written into the location
through A
Revised December 1, 2010
CY7C1011DV33
15
) are placed in a
0
16
through I/O
).
www.cypress.com
8
to I/O
408-943-2600
15
. See
7
), is
0
[+] Feedback

Related parts for CY7C1011DV33-10ZSXI

CY7C1011DV33-10ZSXI Summary of contents

Page 1

... HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1011DV33 is available in standard Pb-free 44-pin TSOP II with center power and ground pinout, as well as 48-ball very fine-pitch ball grid array (VFBGA) packages. ...

Page 2

... Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Waveforms ...................................................... 7 Read Cycle No. 1 ........................................................ 7 Read Cycle No. 2 (OE Controlled) .............................. 7 Write Cycle No. 1 (CE Controlled) ............................... 8 Document Number: 38-05609 Rev. *E CY7C1011DV33 Write Cycle No. 3 (WE Controlled, OE HIGH During Write) ...................................................... 9 Write Cycle No. 4 (WE Controlled, OE LOW) ............. 9 Truth Table ...................................................................... 10 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams ...

Page 3

... TSOP II Top View BHE BLE CE 6 I I I I I/O I I/O I I/O I I/O I 48-ball VFBGA (Top View BLE I/O BHE CE I I/O I/O I I I/O I/O I CY7C1011DV33 Unit Page [+] Feedback ...

Page 4

... > V – 0 < 0 Test Conditions = 25  MHz 3 Test Conditions Still air, soldered × 4.5 inch, four-layer printed circuit board CY7C1011DV33 Ambient V CC Temperature –40 C to +85 C 3.3 V  0.3 V –10 Min Max 2.4 – – 0.4 2 0.3 CC –0.3 0.8 – ...

Page 5

... CC is less than less than HZCE LZCE HZOE LZOE HZBE CY7C1011DV33 ALL INPUT PULSES 90% 10% Fall Time: 1 V/ns (b) –10 Unit Max s – – – – – ...

Page 6

... DATA RETENTION MODE 3 > CDR and t HZWE is less than less than HZCE LZCE HZOE LZOE HZBE > 50 s or stable at V > 50  CC(min.) CC(min.) CY7C1011DV33 –10 Unit Max – ns – ns – ns – ns – ns – ns – ns – ns – – ns Min Max Unit 2 ...

Page 7

... CURRENT Notes 16. Device is continuously selected. OE, CE, BHE and/or BHE = V 17 HIGH for read cycle. 18. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05609 Rev OHA t RC DATA VALID 50 CY7C1011DV33 DATA VALID t HZOE t HZCE t HZBE HIGH IMPEDANCE ICC CC 50% I ISB ...

Page 8

... Write Cycle No. 2 (BLE or BHE Controlled) ADDRESS t SA BHE, BLE WE CE DATA I/O Notes 19. Data I/O is high-impedance BHE and/or BLE = V 20 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05609 Rev SCE PWE PWE t SCE CY7C1011DV33 Page [+] Feedback ...

Page 9

... If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 23. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05609 Rev. *E [21, 22 SCE PWE t SD DATA VALID SCE PWE HZWE CY7C1011DV33 LZWE Page [+] Feedback ...

Page 10

... Data High High Z Ordering Information Speed (ns) Ordering Code 10 CY7C1011DV33-10ZSXI CY7C1011DV33-10BVI CY7C1011DV33-10BVXI Ordering Code Definitions V33 - 10 xxx Please contact your local Cypress sales representative for availability of these parts Document Number: 38-05609 Rev. *E I/O –I/O I/O –I High Z Power-down Data Out Read all bits ...

Page 11

... Package Diagrams Figure 2. 48-ball VFBGA (6 × 8 × 1 mm), 51-85150 Document Number: 38-05609 Rev. *E Figure 1. 44-pin TSOP II, 51-85087 CY7C1011DV33 51-85087 *C 51-85150 *F Page [+] Feedback ...

Page 12

... SRAM static random access memory TSOP thin small-outline package TTL transistor-transistor logic VFBGA very fine-pitch ball grid array WE write enable Document Number: 38-05609 Rev. *E CY7C1011DV33 Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µs micro seconds µA ...

Page 13

... Document History Document Title: CY7C1011DV33 2-Mbit (128 K × 16) Static RAM Document Number: 38-05609 REV. ECN NO. Issue Date ** 250650 See ECN *A 399070 See ECN *B 459073 See ECN *C 480177 See ECN *D 3059162 10/14/2010 *E 3098812 12/01/2010 Document Number: 38-05609 Rev. *E Orig. of Description of Change Change ...

Page 14

... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05609 Rev. *E All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised December 1, 2010 CY7C1011DV33 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...

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