M29W640FB70ZA6E NUMONYX, M29W640FB70ZA6E Datasheet - Page 11
![IC FLASH 64MBIT 70NS 48TFBGA](/photos/7/24/72417/m29w640fb70za6e_sml.jpg)
M29W640FB70ZA6E
Manufacturer Part Number
M29W640FB70ZA6E
Description
IC FLASH 64MBIT 70NS 48TFBGA
Manufacturer
NUMONYX
Series
Axcell™r
Datasheet
1.M29W640FB70ZA6E.pdf
(71 pages)
Specifications of M29W640FB70ZA6E
Format - Memory
FLASH
Memory Type
FLASH - Nor
Memory Size
64M (8Mx8, 4Mx16)
Speed
70ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TFBGA
Package
48TFBGA
Cell Type
NOR
Density
64 Mb
Architecture
Sectored
Block Organization
Asymmetrical
Location Of Boot Block
Bottom
Typical Operating Supply Voltage
3|3.3 V
Sector Size
8KByte x 8|64KByte x 127
Timing Type
Asynchronous
Interface Type
Parallel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-5032
497-5032
497-5032
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M29W640FB70ZA6E
Manufacturer:
Micron Technology Inc
Quantity:
10 000
2
2.1
2.2
2.3
2.4
2.5
2.6
Signal descriptions
See
connected to this device.
Address Inputs (A0-A21)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command Interface
of the Program/Erase Controller.
Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE is High, V
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1)
When BYTE is High, V
When BYTE is Low, V
LSB of the addressed Word, DQ15A–1 High will select the MSB. Throughout the text
consider references to the Data Input/Output to include this pin when BYTE is High and
references to the Address Inputs to include this pin when BYTE is Low except when stated
explicitly otherwise.
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
Figure 1: Logic
diagram, and
IL
IH
IH
, this pin behaves as an address pin; DQ15A–1 Low will select the
. When BYTE is Low, V
, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
Table 2: Signal
IH
, all other pins are ignored.
IL
, these pins are not used and are high
names, for a brief overview of the signals
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