CY7C1021BNV33L-15ZXI Cypress Semiconductor Corp, CY7C1021BNV33L-15ZXI Datasheet - Page 7

• Manufacturer Part Number: CY7C1021BNV33L-15ZXI
• Description: IC SRAM 1MBIT 15NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C1021BNV33L-15ZXI

• Memory Size: 1M (64K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 15 ns
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Current: 160 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3.3 V
• Density: 1Mb
• Access Time (max): 15ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Supply Current: 160mA
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 64K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Document #: 001-06433 Rev. *C
Notes
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
5. t
6. At any given temperature and voltage condition, t
7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
I
500 mV from steady-state voltage.
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
OL
HZOE
Parameter
/I
OH
, t
HZBE
and 30-pF load capacitance.
, t
HZCE
[7]
, and t
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write
HZWE
are specified with a load capacitance of 5 pF as in part (b) of
[4]
[6]
HZCE
[5, 6]
[6]
[5, 6]
[5, 6]
is less than t
Description
LZCE
, t
HZOE
is less than t
LZOE
AC Test Loads and Waveforms on page
, and t
HZWE
is less than t
LZWE
Min
15
15
10
10
10
CY7C1021BNV33
–
3
–
–
0
–
3
–
0
–
–
0
–
0
0
8
0
3
–
9
for any given device.
-15
6. Transition is measured
Max
15
15
15
–
–
7
–
7
–
7
–
7
–
7
–
–
–
–
–
–
–
–
–
7
–
Page 7 of 17
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback