MAX802LESA+T Maxim Integrated, MAX802LESA+T Datasheet - Page 4

• Manufacturer Part Number: MAX802LESA+T
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX690A, MAX692A, MAX802L, MAX802M, MAX805Lr

Specifications of MAX802LESA+T

• Number Of Voltages Monitored: 1
• Monitored Voltage: 4.65 V
• Undervoltage Threshold: 4.5 V
• Overvoltage Threshold: 4.75 V
• Output Type: Active Low, Push-Pull
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Narrow
• Chip Enable Signals: No
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Supply Current (typ): 500 uA
• Supply Voltage - Min: 1.2 V

+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
(V
4
______________________________________________________________Pin Description
12, 13, 16,
____________________________Typical Operating Characteristics (continued)
9, 17, 18,
1, 3, 5, 7
2, 4, 6, 8
CC
19, 24,
20, 21,
25, 32
28, 29
_______________________________________________________________________________________
-2
-4
PIN
4
2
0
6
10
11
14
15
22
23
26
27
30
31
= +3.0V to +3.6V, differential LVDS loads = 100Ω, unless otherwise noted.)
-50
-25
PD0+ to PD3+
PD0- to PD3-
PCLKO-to-PCLKI SKEW
PCLKO+
PCLKO-
PCLKI+
vs. TEMPERATURE
RCLK+
PCLKI-
NAME
RCLK-
TEMPERATURE (°C)
GND
SD+
FIL+
V
0
SD-
FIL-
CC
25
50
Noninverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
Inverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
Ground
Inverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit.
Noninverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit.
+3.3V Supply Voltage
Inverting PECL Serial-Data Output
Noninverting PECL Serial-Data Output
Filter Capacitor Input. See Typical Operating Circuit for external-component connections.
Filter Capacitor Input. See Typical Operating Circuit for external-component connections.
Noninverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock
(155.52MHz) to the RCLK inputs.
Inverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock (155.52MHz)
to the RCLK inputs.
Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the
PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
Inverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI
inputs. Note that data is updated on the positive transition of the PCLKI signal.
75
100
62mV/
1.21V
0.59V
div
SERIAL-DATA OUTPUT EYE DIAGRAM
(622Mbps, 2
161ps/div
7
-1 PRBS)
SONET MASK
OC-12
FUNCTION
908mV
808mV
10mV/
div
Mean 23.88ns
RMS∆ 8.418ps
PkPk 70.2ps
SERIAL-DATA OUTPUT JITTER
10ps/div
f
RCLK
= 155.52MHz
µ±1σ 68.774%
µ±2σ 95.534%
µ±3σ 99.738%