CY62126EV30LL-45ZSXI Cypress Semiconductor Corp, CY62126EV30LL-45ZSXI Datasheet - Page 7

• Manufacturer Part Number: CY62126EV30LL-45ZSXI
• Description: IC SRAM 1MBIT 45NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62126EV30LL-45ZSXI

• Memory Size: 1M (64K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 16 mA
• Organization: 64 K x 16
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V or 3.3 V
• Memory Configuration: 64K X 16
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2063; CY62126EV30LL-45ZSXI

Switching Characteristics
Over the Operating Range
Document #: 38-05486 Rev. *H
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
13. At any temperature and voltage condition, t
14. t
15. The internal write time of the memory is defined by the overlap of WE, CE = V
Parameter
I
signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
OL
HZOE
/I
OH
, t
and 30-pF load capacitance.
HZCE
[15]
, t
HZBE
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to power up
CE HIGH to power down
BHE / BLE LOW to data valid
BHE / BLE LOW to Low Z
BHE / BLE HIGH to High Z
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BHE / BLE pulse width
Data setup to write end
Data hold from write end
WE LOW to High Z
WE HIGH to Low Z
, and t
HZWE
[11, 12]
transitions are measured when the outputs enter a high impedance state.
Description
[13]
[13]
HZCE
[13, 14]
[13, 14]
[13]
[13, 14]
is less than t
[13]
[13, 14]
LZCE
, t
HZBE
is less than t
45 ns (Industrial)
Min
45
10
10
45
35
35
35
35
25
10
–
–
–
5
–
–
0
–
–
5
–
0
0
0
–
IL
, BHE, BLE or both = V
LZBE
CC(typ)
, t
Max
HZOE
45
45
22
18
18
45
22
18
18
/2, input pulse levels of 0 to V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
is less than t
IL
. All signals must be active to initiate a write and any of these
55 ns (Automotive)
Min
55
10
10
55
40
40
40
40
25
10
LZOE
–
–
–
5
–
–
0
–
–
5
–
0
0
0
–
application note AN13842
, and t
CY62126EV30 MoBL
CC(typ)
HZWE
Max
is less than t
55
55
25
20
20
55
25
20
20
, and output loading of the specified
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
for further clarification.
LZWE
Unit
for any device.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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