CY62256NLL-55SNXI Cypress Semiconductor Corp, CY62256NLL-55SNXI Datasheet - Page 6

• Manufacturer Part Number: CY62256NLL-55SNXI
• Description: IC SRAM 256KBIT 55NS 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62256NLL-55SNXI

• Memory Size: 256K (32K x 8)
• Package / Case: 28-SOIC (7.5mm Width)
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 55 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 50 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Memory Configuration: 32K X 8
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: NSOIC
• No. Of Pins: 28
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2083-5; CY62256NLL-55SNXI

Switching Characteristics
Over the Operating Range
Switching Waveforms
Document Number: 001-06511 Rev. *D
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
10. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
11. At any temperature and voltage condition, t
12. t
13. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
14. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
15. Device is continuously selected. OE, CE = V
16. WE is HIGH for Read cycle.
Parameter
DATA OUT
ADDRESS
I
terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.
OL
HZOE
/I
OH
, t
and 100-pF load capacitance.
HZCE
[13, 14]
, and t
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power up
CE HIGH to power down
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE LOW to high Z
WE HIGH to low Z
HZWE
are specified with C
PREVIOUS DATA VALID
[10]
Description
[11]
[11]
[11]
[11, 12]
[11, 12]
[11, 12]
HZCE
L
IL
.
= 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
t
is less than t
OHA
Figure 5. Read Cycle No. 1
t
AA
LZCE
, t
HZOE
Min
55
55
45
45
40
25
–
5
–
–
5
–
5
–
0
–
0
0
0
–
5
is less than t
CY62256N-55
t
RC
LZOE
Max
HZWE
, and t
55
55
25
20
20
55
20
[15, 16]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
and t
HZWE
SD
is less than t
.
Min
70
70
60
60
50
30
–
5
–
–
5
–
5
–
0
–
0
0
0
–
5
CY62256N-70
LZWE
DATA VALID
for any device.
Max
70
70
35
25
25
70
25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY62256N
Unit
Page 6 of 14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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