CY62256VNLL-70SNXI Cypress Semiconductor Corp, CY62256VNLL-70SNXI Datasheet - Page 8

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CY62256VNLL-70SNXI

Manufacturer Part Number
CY62256VNLL-70SNXI
Description
IC SRAM 256KBIT 70NS 28SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr

Specifications of CY62256VNLL-70SNXI

Memory Size
256K (32K x 8)
Package / Case
28-SOIC (7.5mm Width)
Format - Memory
RAM
Memory Type
SRAM
Speed
70ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Access Time
70 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
30 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
3 V
Memory Configuration
32K X 8
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
NSOIC
No. Of Pins
28
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2001-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62256VNLL-70SNXI
Manufacturer:
CYPRESS
Quantity:
3 520
Part Number:
CY62256VNLL-70SNXI
Manufacturer:
CYPRESS
Quantity:
63
Part Number:
CY62256VNLL-70SNXI
Manufacturer:
HP
Quantity:
131
Part Number:
CY62256VNLL-70SNXIT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Switching Waveforms
Notes
Document Number: 001-06512 Rev. *D
21. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
22. Data I/O is high impedance if OE = V
23. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
24. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
25. During this period, the I/Os are in output state and input signals should not be applied.
ADDRESS
ADDRESS
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
DATA I/O
DATA I/O
CE
WE
CE
WE
t
SA
NOTE 25
(continued)
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)
IH
.
Figure 6. Write Cycle No. 2 (CE Controlled)
t
HZWE
t
SA
t
t
AW
AW
t
WC
t
WC
DATA
DATA
t
HZWE
SCE
t
SD
t
SD
IN
and t
IN
VALID
VALID
SD
[21, 22, 23]
.
[23, 24]
t
HD
t
t
HA
t
LZWE
HA
t
HD
CY62256VN
Page 8 of 14
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