M95512-RMN6TP STMicroelectronics, M95512-RMN6TP Datasheet - Page 30
![IC EEPROM 512KBIT 2MHZ 8SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
M95512-RMN6TP
Manufacturer Part Number
M95512-RMN6TP
Description
IC EEPROM 512KBIT 2MHZ 8SOIC
Manufacturer
STMicroelectronics
Specifications of M95512-RMN6TP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
512K (64K x 8)
Speed
2MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Density
512Kb
Interface Type
Serial (SPI)
Organization
64Kx8
Access Time (max)
150ns
Frequency (max)
2MHz
Write Protection
Yes
Data Retention
40Year
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Temp Range
-40C to 85C
Supply Current
3mA
Operating Supply Voltage (min)
1.8V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6356-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M95512-RMN6TP
Manufacturer:
TDK
Quantity:
324
ECC (error correction code) and write cycling
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8
8.1
8.2
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ECC (error correction code) and write cycling
The M95512-W, M95512-R and M95512-DR devices offer an ECC (error correction code)
logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a
result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation,
the ECC detects it and replaces it by the correct value. The read reliability is therefore much
improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes
making up the word. It is therefore recommended to write data by word (4 bytes) at address
4*N (where N is an integer) in order to benefit from the larger amount of Write cycles.
The M95512-W, M95512-R and M95512-DR devices are qualified at 1 million (1 000 000)
Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets.
Power-up and delivery state
Power-up state
After power-up, the device is in the following state:
●
●
●
●
●
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
Standby Power mode
Deselected (after Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
Not in the Hold Condition
Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
Doc ID 11124 Rev 14
M95512-DR, M95512-W, M95512-R