M24256-BWMN6TP STMicroelectronics, M24256-BWMN6TP Datasheet - Page 21

• Manufacturer Part Number: M24256-BWMN6TP
• Description: IC EEPROM 256KBIT 400KHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M24256-BWMN6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Density: 256Kb
• Interface Type: Serial (I2C)
• Organization: 32Kx8
• Access Time (max): 900ns
• Frequency (max): 400KHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Supply Current: 5mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8623-2; M24256-BWMN6TP

M24256-BF, M24256-BR, M24256-BW, M24256-DR
3.15
3.16
3.17
Current Address Read (in memory array)
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
Read Identification Page
This instruction uses the same protocol and format as the
memory array)
Read Identification Page instruction:
●
●
the device type identifier = 1011b
MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A5/A0 define the byte address inside the identification page. During a
Read Identification Page instruction, the (A5/A0) address should not exceed 3Fh.
11, without acknowledging the byte.
instruction. The only differences between the two instructions are that, in the
Figure
11.
Doc ID 6757 Rev 21
Random Address Read (in
Device operation
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