IS42S32400D-7TL ISSI, Integrated Silicon Solution Inc, IS42S32400D-7TL Datasheet - Page 11
![IC SDRAM 128MBIT 143MHZ 86TSOP](/photos/7/23/72320/is42s32400d-7tl_sml.jpg)
IS42S32400D-7TL
Manufacturer Part Number
IS42S32400D-7TL
Description
IC SDRAM 128MBIT 143MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S32400D-7TL.pdf
(60 pages)
Specifications of IS42S32400D-7TL
Package / Case
86-TSOPII
Memory Size
128M (4Mx32)
Format - Memory
RAM
Memory Type
SDRAM
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
32 bit
Maximum Clock Frequency
143 MHz
Access Time
6.5 ns, 5.4 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
130 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1023
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32400D-7TL
Manufacturer:
ISSI
Quantity:
1 000
Company:
Part Number:
IS42S32400D-7TL
Manufacturer:
ISSI
Quantity:
1 000
Company:
Part Number:
IS42S32400D-7TL
Manufacturer:
ISSI
Quantity:
26
Part Number:
IS42S32400D-7TL
Manufacturer:
ISSI
Quantity:
20 000
Company:
Part Number:
IS42S32400D-7TLI-TR
Manufacturer:
ISSI
Quantity:
1 000
IS42S32400D
FUNCTIONAL TRUTH TABLE Continued:
Current State
Write Recovering
Write Recovering
with Auto
Precharge
Refresh
Mode Register
Accessing
Note: H=V
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
03/03/09
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.
be disabled.
state of that bank.
be disabled.
IH
, L=V
IL
x= V
CS
CS
CS
CS
CS
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
IH
or V
H
H
H
H
L
L
L
L
×
H
H
H
H
L
L
L
L
×
H
H
H
L
L
L
L
H
H
H
L
RAS
RAS
RAS
RAS
RAS CAS
×
×
IL
, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
CAS
CAS
CAS
CAS
H
H
L
L
H
H
L
L
×
H
H
L
L
H
H
L
L
×
H
L
L
H
H
L
L
H
H
L
×
×
×
×
H
L
H
L
H
L
H
L
×
H
L
H
L
H
L
H
L
H
L
H
L
H
L
×
H
L
×
×
WE
WE
WE
WE
WE
×
×
Address
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
OC, BA
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
BA, CA, A10
BA, RA
×
×
×
Command
DESL
NOP
BST
READ/READA
WRIT/ WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/WRITE
ACT/PRE/PALL
REF/MRS
Action
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Begin read
Begin new write
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop, Enter precharge after tDPL
Nop, Enter precharge after tDPL
Nop, Enter row active after tDPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop, Enter idle after tRC
Nop, Enter idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop, Enter idle after 2 clocks
Nop, Enter idle after 2 clocks
ILLEGAL
ILLEGAL
ILLEGAL
(3,8,11)
(3)
(3)
(3,11)
(3,11)
(3,11)
(8)
11