7024S55J8 IDT, 7024S55J8 Datasheet - Page 9

• Manufacturer Part Number: 7024S55J8
• Description: SRAM
• Manufacturer: IDT

Specifications of 7024S55J8

• Part # Aliases: IDT7024S55J8

Waveform of Read Cycles
NOTES:
1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. t
4. Start of valid data depends on which timing becomes effective last t
5. SEM = V
Timing of Power-Up Power-Down
BUSY
DATA
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
no relation to valid output data.
UB, LB
BDD
ADDR
R/W
delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has
OUT
OUT
OE
CE
IH
.
I
I
CE
CC
SB
t
t
t
t
t
AA
ACE
AOE
LZ
ABE
(4)
(1)
(5)
(4)
(4)
(4)
t
PU
ABE
t
, t
RC
AOE
, t
6.42
t
ACE
9
BDD
, t
VALID DATA
AA
(3,4)
or t
BDD
Military, Industrial and Commercial Temperature Ranges
.
t
PD
(4)
2740 drw 08
,
t
HZ
t
OH
(2)
2740 drw 07