MT48H4M16LFB4-75 IT:H TR Micron Technology Inc, MT48H4M16LFB4-75 IT:H TR Datasheet - Page 24

• Manufacturer Part Number: MT48H4M16LFB4-75 IT:H TR
• Description: IC SDRAM 64MBIT 133MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-75 IT:H TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1391-2

WRITEs
Figure 16:
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
WRITE Command
Fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x equals the CL minus one. This is shown in Figure 15 on page 23 for each
possible CL; data element n + 3 is the last desired data element of a longer burst.
WRITE bursts are initiated with a WRITE command, as shown in Figure 16.
The starting column and bank addresses are provided with the WRITE command and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQ will remain High-Z and any additional input
data will be ignored (see Figure 18 on page 25).
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 19 on page 26. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The Mobile SDRAM uses a pipe-
lined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
Address
BA0, BA1
RAS#
CAS#
WE#
CKE
A10
CLK
CS#
HIGH
Valid Address
Disable auto precharge
Enable auto precharge
Address
Column
Address
Bank
24
Don’t Care
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: 4 Meg x 16 Mobile SDRAM
©2006 Micron Technology, Inc. All rights reserved.
Operations