70V25L25PFI8 IDT, 70V25L25PFI8 Datasheet - Page 18

• Manufacturer Part Number: 70V25L25PFI8
• Description: SRAM 8Kx16, 3.3V DUAL- PORT RAM
• Manufacturer: IDT

Specifications of 70V25L25PFI8

• Part # Aliases: IDT70V25L25PFI8

ADDR
ADDR
Timing Waveform of Write with BUSY
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. t
Waveform of BUSY Arbitration Controlled by CE Timing
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing
BUSY
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If t
ADDR
BUSY
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
and
CE
CE
WH
WB
APS
"A"
"B"
"B"
"A"
"B"
"A"
"B"
"B"
must be met for both master BUSY input (slave) and output (master).
is only for the slave version.
is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
(1)
(M/S = V
BUSY
R/W
R/W
t
APS
(2)
"A"
"B"
"B"
IH
t
)
APS
"B"
(2)
, until BUSY
t
BAA
ADDRESS "N"
MATCHING ADDRESS "N"
"B"
t
WB
goes HIGH.
t
BAC
(3)
ADDRESSES MATCH
6.42
18
t
WP
(2)
Industrial and Commercial Temperature Ranges
t
BDC
t
BDA
t
WH
(1)
5624 drw 14
(1)
(M/S = V
,
IH
)
5624 drw 15
5624 drw 16