IS61C1024AL-12JLI ISSI, Integrated Silicon Solution Inc, IS61C1024AL-12JLI Datasheet - Page 7
![IC SRAM 1MBIT 12NS 32SOJ](/photos/7/22/72272/is61c1024al-12jli_sml.jpg)
IS61C1024AL-12JLI
Manufacturer Part Number
IS61C1024AL-12JLI
Description
IC SRAM 1MBIT 12NS 32SOJ
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
Asynchronousr
Datasheet
1.IS61C1024AL-12JLI.pdf
(17 pages)
Specifications of IS61C1024AL-12JLI
Memory Size
1M (128K x 8)
Package / Case
32-SOJ
Interface
Parallel
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Speed
12ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Access Time
12 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Current
40 mA
Organization
128 K x 8
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
5 V
Density
1Mb
Access Time (max)
12ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
17b
Package Type
SOJ
Operating Temp Range
-40C to 85C
Supply Current
40mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Number Of Words
128K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1028
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS61C1024AL-12JLI
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS61C1024AL-12JLI
Manufacturer:
ISSI
Quantity:
20 000
IS61C1024AL, IS64C1024AL
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
3. Tested with OE HIGH.
4. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. B
01/24/05
Symbol
t
t
t
t
t
t
t
t
t
t
t
and output loading specified in Figure 1.
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
WC
SCE
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
1
2
(3)
(4)
(4)
Parameter
Write Cycle Time
CE1 to Write End
CE2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
1-800-379-4774
Min. Max.
12
10
10
10
10
—
0
0
7
0
2
(1,2)
-12 ns
(Over Operating Range, Standard and Low Power)
—
—
—
—
—
—
—
—
—
—
7
Min. Max.
15
12
12
12
12
10
—
0
0
0
2
-15 ns
—
—
—
—
—
—
—
—
—
—
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISSI
®
7